Parallel Responsive Task on Dependable Responsive Multithreaded Processor II

Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle), processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effectively reduces the cache size available to each individual thread. Increased processor utilization and the increase in the cache miss rate demands higher memory bandwidth. A novel compiler optimization method has been presented in this paper that improves data locality for each of the threads and enhances data sharing among the threads. The method is based on loop transformation theory and optimizes both spatial and temporal data locality. The created threads exhibit high level of intra‐thread and inter‐thread data locality which effectively reduces both the data cache miss rates and the total execution time of numerically intensive computation running on a multithreaded processor.

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A case for the multithreaded processor architecture

ACM SIGARCH Computer Architecture News ◽

10.1145/190787.190806 ◽

1994 ◽

Vol 22 (4) ◽

pp. 55-59

Author(s):

Ghulam Chaudhry ◽

Xuechang Li

Keyword(s):

Processor Architecture ◽

Multithreaded Processor

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Design and Implementation of the Multimedia Operation Mechanism for Responsive Multithreaded Processor

Journal of Robotics and Mechatronics ◽

10.20965/jrm.2005.p0456 ◽

2005 ◽

Vol 17 (4) ◽

pp. 456-462 ◽

Cited By ~ 3

Author(s):

Tsutomu Itou ◽

◽

Nobuyuki Yamasaki ◽

Keyword(s):

Real Time ◽

High Performance ◽

Multimedia Data ◽

Multimedia Processing ◽

Operation Mechanism ◽

Vector Operation ◽

Multithreaded Processor ◽

Hard Real Time ◽

Time Systems ◽

Processing Architecture

Responsive Multithreaded (RMT) Processor is designed for distributed real-time systems. This paper focuses on the multimedia processing architecture of RMT Processor. Multimedia processing requires high-throughput calculation for bulky data processing. RMT Processor architecture is based on eight-way prioritized simultaneous multithreading, which executes each thread in order of priority. Since the priority of hard real-time threads is higher than that of multimedia processing threads, instruction issue slots used by the multimedia processing threads are few in RMT Processor when hard real-time threads are executed simultaneously. Therefore multimedia processing threads need to utilize instruction issue slots effectively to achieve high performance. We have designed a novel vector operation mechanism to process multimedia data efficiently in parallel. Because the same instructions are iterated in multimedia processing, the compound operation mechanism is designed to calculate more data per instruction in multimedia processing.

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