A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors

Author(s):  
Yasuhisa Shimazaki ◽  
Noriyuki Miura ◽  
Tadahiro Kuroda
CIRP Annals ◽  
2010 ◽  
Vol 59 (1) ◽  
pp. 167-170 ◽  
Author(s):  
Y.H. Yin ◽  
C. Zhou ◽  
J.Y. Zhu

2003 ◽  
Vol 84 (2) ◽  
pp. 303-303
Author(s):  
Maurice Bernaiche ◽  
Michael Andary
Keyword(s):  

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