A middle ground between CAMs and DAGs for high-speed packet classification

2003 ◽  
Author(s):  
A. Prakash ◽  
A. Aziz
Keyword(s):  
High Speed ◽  
Packet Classification ◽  
Middle Ground

Efficient Memristor-Based Architecture for Intrusion Detection and High-Speed Packet Classification

2018 ◽  
Vol 14 (4) ◽  
pp. 1-27 ◽  
Author(s):  
Venkataramesh Bontupalli ◽  
Chris Yakopcic ◽  
Raqibul Hasan ◽  
Tarek M. Taha
Keyword(s):  
Intrusion Detection ◽  
High Speed ◽  
Packet Classification

scholarly journals Wildcard Fields-Based Partitioning for Fast and Scalable Packet Classification in Vehicle-to-Everything

Sensors ◽  
2019 ◽  
Vol 19 (11) ◽  
pp. 2563 ◽  
Author(s):  
Jaehyung Wee ◽  
Jin-Ghoo Choi ◽  
Wooguil Pak
Keyword(s):  
Decision Tree ◽  
Communication Networks ◽  
High Speed ◽  
Classification Performance ◽  
Packet Classification ◽  
Classification Algorithms ◽  
Packet Processing ◽  
Security Issues ◽  
Security Of Network ◽  
High Level

Vehicle-to-Everything (V2X) requires high-speed communication and high-level security. However, as the number of connected devices increases exponentially, communication networks are suffering from huge traffic and various security issues. It is well known that performance and security of network equipment significantly depends on the packet classification algorithm because it is one of the most fundamental packet processing functions. Thus, the algorithm should run fast even with the huge set of packet processing rules. Unfortunately, previous packet classification algorithms have focused on the processing speed only, failing to be scalable with the rule-set size. In this paper, we propose a new packet classification approach balancing classification speed and scalability. It can be applied to most decision tree-based packet classification algorithms such as HyperCuts and EffiCuts. It determines partitioning fields considering the rule duplication explicitly, which makes the algorithm memory-effective. In addition, the proposed approach reduces the decision tree size substantially with the minimal sacrifice of classification performance. As a result, we can attain high-speed packet classification and scalability simultaneously, which is very essential for latest services such as V2X and Internet-of-Things (IoT).

A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification

2009 ◽  
Vol 56 (9) ◽  
pp. 729-733 ◽  
Author(s):  
Jian-Wei Zhang ◽  
Ming-Yan Yu ◽  
Bin-Da Liu ◽  
Xiao-Feng Huang
Keyword(s):  
High Speed ◽  
Packet Classification

scholarly journals Design of a Low Latency and High Throughput Packet Classification Module on FPGA Platform

2020 ◽  
Vol 9 (4) ◽  
pp. 1468-1474
Keyword(s):  
High Speed ◽  
Network Performance ◽  
Packet Classification ◽  
Total Power ◽  
Network Systems ◽  
Chip Area ◽  
Packet Header ◽  
Rule Set ◽  
Bit Vector ◽  
Ip Packet

The Packet classification method plays a significant role in most of the Network systems. These systems categories the incoming packets in various flows and takes suitable action based on the requirements. If the size of the network is vast and complexity will arise to perform the different operations, which affects the network performance and other constraints also. So there is the demand for high-speed packet classifiers to reduce the network complexity and improve the network performance. In this article, The Bit vector Packet classifier (BV-PC) Module is designed to improve the network system performance and overcome the existing limitation of Packet classification approaches on FPGA. The BV-PC Module contains Packet generation Unit (PGU) to receive the valid incoming packets, Memory Unit (MU) to store valid packets, Header Extractor Unit (HEU) extracts the IP Header address information from the Valid packets, The BV-Based Source and Destination Address (BV-SA, BV-DA) unit receives the IP packet header Information and Process with BV based rule set and aggregates the BV-SA and BV-DA outputs, Priority Encoder encodes the Highest priority BV Rule for the generation of Classified output. The BV-PC utilizes <2% Chip area (slices), works at 509.38MHz, and consumed Less 0.103 W of total Power on Artix-7 FPGA. The BV-PC operates with a latency of 5 clock cycles and works at 815.03Mpps throughput. The BV-PC is compared with existing approaches and provides Better improvements in Hardware constraints.

scholarly journals Enhancing the performance of the aggregated bit vector algorithm in network packet classification using GPU

2019 ◽  
Vol 5 ◽  
pp. e185 ◽  
Author(s):  
Mahdi Abbasi ◽  
Razieh Tahouri ◽  
Milad Rafiee
Keyword(s):  
Graphics Processing Units ◽  
High Speed ◽  
Parallel Implementation ◽  
Packet Classification ◽  
Experimental Results ◽  
Analysis Method ◽  
Network Systems ◽  
Computationally Intensive ◽  
Bit Vector ◽  
Graphics Processing

Packet classification is a computationally intensive, highly parallelizable task in many advanced network systems like high-speed routers and firewalls that enable different functionalities through discriminating incoming traffic. Recently, graphics processing units (GPUs) have been exploited as efficient accelerators for parallel implementation of software classifiers. The aggregated bit vector is a highly parallelizable packet classification algorithm. In this work, first we present a parallel kernel for running this algorithm on GPUs. Next, we adapt an asymptotic analysis method which predicts any empirical result of the proposed kernel. Experimental results not only confirm the efficiency of the proposed parallel kernel but also reveal the accuracy of the analysis method in predicting important trends in experimental results.

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