Design of multi-channel high speed sampling data transmission and reception

2017 ◽  
Author(s):  
Yang Mingfei ◽  
Yuan Guoping
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
High Speed Sampling

Analysis of Inter-Satellite Optical Wireless Communication System

2017 ◽  
Vol 7 (10) ◽  
pp. 10
Author(s):  
Rajbir Singh
Keyword(s):  
Wireless Communication ◽  
Optical Networks ◽  
Data Transmission ◽  
High Speed ◽  
Open Space ◽  
Communication Link ◽  
Optical Wireless Communication ◽  
Optical Wireless ◽  
High Speed Data ◽  
Speed Data Transmission

Optical networks are bandwidth efficient networks are used for long haul communication providing seamless data transfer. For high speed data transmission in open space between different satellites, Inter-satellite Optical wireless communication (IsOWC) is widely used .In this paper we have evaluated the performance of IsOWC communication link for high speed data transmission .The performance of the system is evaluated on the basis of qualitative parameters such as Q-factor and BER using optisystem simulator.

Top-down Fabricated Gold Nanostrip on Silicon-on-insulator Wafer: A Promising Building Block towards Ultra-compact Optical Device

Nanoscale ◽  
2020 ◽  
Author(s):  
Fuping Zhang ◽  
Weikang Liu ◽  
Li Chen ◽  
Zhiqiang Guan ◽  
Hongxing Xu
Keyword(s):  
Optical Communication ◽  
Data Transmission ◽  
Building Block ◽  
High Speed ◽  
Large Data ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Fundamental Building Block ◽  
Low Energy Consumption ◽  
Controllable Fabrication

he plasmonic waveguide is the fundamental building block for high speed, large data transmission capacity, low energy consumption optical communication and sensing. Controllable fabrication and simultaneously optimization of the propagation...

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

A Dicode Signaling Scheme for Capacitively Coupled Interface

2011 ◽  
Vol 497 ◽  
pp. 296-305
Author(s):  
Yasushi Yuminaka ◽  
Kyohei Kawano
Keyword(s):  
Partial Response ◽  
Data Transmission ◽  
High Speed ◽  
Circuit Simulation ◽  
Frequency Bandwidth ◽  
Capacitively Coupled ◽  
Limited Frequency ◽  
Simulation Results ◽  
Response Coding ◽  
The Impact

In this paper, we present a bandwidth-efficient partial-response signaling scheme for capacitivelycoupled chip-to-chip data transmission to increase data rate. Partial-response coding is knownas a technique that allows high-speed transmission while using a limited frequency bandwidth, by allowingcontrolled intersymbol interference (ISI). Analysis and circuit simulation results are presentedto show the impact of duobinary (1+D) and dicode (1-D) partial-response signaling for capacitivelycoupled interface.

The Design and Implementation of ECC High-Speed Encryption Engine Based on FPGA

2012 ◽  
Vol 459 ◽  
pp. 544-548 ◽  
Author(s):  
Wei Liang ◽  
Jian Bo Xu ◽  
Wei Hong Huang ◽  
Li Peng
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Lower Cost ◽  
Low Cost ◽  
Rapid Development ◽  
Security Technology ◽  
Multiplication Algorithm ◽  
Secure Data Transmission ◽  
And Performance ◽  
Computation Speed

Network security technology ensures secure data transmission in network. Meanwhile, it brings extra overhead of security system in terms of cost and performance, which seriously affects the rapid development of existing high-speed encryption systems. The existing encryption technology cannot meet the demand of high security, low cost and high real-time. For solving above problems, an ECC encryption engine architecture based on scalable public key cipher and a high-speed configurable multiplication algorithm are designed. The algorithm was tested on FPGA platform and the experiment results show that the system has better computation speed and lower cost overhead. By comparing with other systems, our system has benefits in terms of hardware overhead and encryption time ratio

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