Microarchitecture of HaL's memory management unit

2002 ◽  
Author(s):  
D.C.-W. Chang ◽  
D. Lyon ◽  
C. Chen ◽  
L. Peng ◽  
M. Massoumi ◽  
...  
Keyword(s):  
Memory Management ◽  
Management Unit

scholarly journals Online Thread and Data Mapping Using a Sharing-Aware Memory Management Unit

2021 ◽  
Vol 5 (4) ◽  
pp. 1-28
Author(s):  
Eduardo H. M. Cruz ◽  
Matthias Diener ◽  
Laércio L. Pilla ◽  
Philippe O. A. Navaux
Keyword(s):  
Energy Efficiency ◽  
Memory Management ◽  
Substantial Reduction ◽  
Management Unit ◽  
Memory Access ◽  
Parallel Applications ◽  
Data Mapping ◽  
Wide Range ◽  
Memory Accesses ◽  
Level Parallelism

Current and future architectures rely on thread-level parallelism to sustain performance growth. These architectures have introduced a complex memory hierarchy, consisting of several cores organized hierarchically with multiple cache levels and NUMA nodes. These memory hierarchies can have an impact on the performance and energy efficiency of parallel applications as the importance of memory access locality is increased. In order to improve locality, the analysis of the memory access behavior of parallel applications is critical for mapping threads and data. Nevertheless, most previous work relies on indirect information about the memory accesses, or does not combine thread and data mapping, resulting in less accurate mappings. In this paper, we propose the Sharing-Aware Memory Management Unit (SAMMU), an extension to the memory management unit that allows it to detect the memory access behavior in hardware. With this information, the operating system can perform online mapping without any previous knowledge about the behavior of the application. In the evaluation with a wide range of parallel applications (NAS Parallel Benchmarks and PARSEC Benchmark Suite), performance was improved by up to 35.7% (10.0% on average) and energy efficiency was improved by up to 11.9% (4.1% on average). These improvements happened due to a substantial reduction of cache misses and interconnection traffic.

The Design of Single Chip Memory Management Unit/Data Cache

1988 ◽  
Author(s):  
A. K. Goksel ◽  
R. H. Krambeck ◽  
P. P. Thomas ◽  
M. S. Tsay
Keyword(s):  
Memory Management ◽  
Management Unit ◽  
Data Cache ◽  
Single Chip

A 6-ns cycle 256-kb cache memory and memory management unit

1993 ◽  
Vol 28 (11) ◽  
pp. 1078-1083 ◽  
Author(s):  
R.A. Heald ◽  
J.C. Holst
Keyword(s):  
Memory Management ◽  
Management Unit ◽  
Cache Memory

The architecture of a memory management unit for object-oriented systems

1991 ◽  
Vol 19 (4) ◽  
pp. 109-116 ◽  
Author(s):  
Alberto R. Cunha ◽  
Carlos N. Ribeiro ◽  
José A. Marques
Keyword(s):  
Memory Management ◽  
Object Oriented ◽  
Management Unit ◽  
Object Oriented Systems
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