A Bypass Optimization Method for Network on Chip

2010 ◽  
Author(s):  
Wei Hu ◽  
Binbin Wu ◽  
Bin Xie ◽  
Tianzhou Chen ◽  
Lianghua Miao
Keyword(s):  
Optimization Method ◽  
Network On Chip ◽  
On Chip

A Topology Optimization Method of Application-Specific Network-on-Chip

2012 ◽  
Vol 457-458 ◽  
pp. 905-912
Author(s):  
Guo Ming Lai ◽  
Xiao La Lin
Keyword(s):  
Network Topology ◽  
Optimization Method ◽  
Network On Chip ◽  
Optimal Topology ◽  
Single Chip ◽  
Communication Problems ◽  
On Chip ◽  
Application Specific ◽  
Total Network ◽  
Topology Optimization Method

Future high-end System-on-chips (SoCs) will be consisted of hundreds of cores integrated on a single chip. On-chip communication becomes the major performance bottleneck of SoCs. Network-on-Chip (NoCs) have become as the most prominent solution to on-chip communication problems. Network topology which affects the total network conformance is basic of network related researches. The objective of topology synthesis is to minimize the power consumption and router resources while satisfying bandwidth constraints. In this paper, we present a two-level genetic-algorithm (GA) based technique to synthesize application-specific NoC topology. Comparing to an existing three-level GA, experiments show that our technique saves 1.8% energy while saving great runtimes of 97.79%. Our technique generates approximate optimal topology less than one minute.

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip
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