Improved Design and Analyse of Parallel Matrix Multiplication on Systolic Array Matrix

2009 ◽  
Author(s):  
Feifei Dong ◽  
Sihan Zhang ◽  
Cheng Chen
Keyword(s):  
Systolic Array ◽  
Matrix Multiplication ◽  
Improved Design

scholarly journals Latency Analysis in the 2-Dimensional Systolic Arrays for Matrix Multiplication

2021 ◽  
Vol 15 ◽  
pp. 1-7
Author(s):  
Halil Snopce ◽  
Azir Aliu
Keyword(s):  
Lower Bound ◽  
Systolic Array ◽  
Matrix Multiplication ◽  
Systolic Arrays ◽  
Latency Analysis

This paper deals with the latency analysis in a twodimensional systolic array for matrix multiplication. The latency for all possible connection schemes is discussed. In this way there is obtained the lower bound of the latency that can be achieved using such arrays.

scholarly journals Mapping matrix multiplication algorithm onto fault-tolerant systolic array

2004 ◽  
Vol 48 (1-2) ◽  
pp. 275-289 ◽  
Author(s):  
N.M. Stojanović ◽  
E.I. Milovanović ◽  
I. Stojmenović ◽  
T.. Milovanović ◽  
T.I. Tokić
Keyword(s):  
Systolic Array ◽  
Fault Tolerant ◽  
Matrix Multiplication ◽  
Matrix Multiplication Algorithm ◽  
Multiplication Algorithm
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