Detailed circuit simulation during switching transient of GTO circuit

2002 ◽  
Author(s):  
H. Sumi ◽  
S. Kobayashi ◽  
M. Morimoto ◽  
S. Sugimoto ◽  
T. Ise
Keyword(s):  
Circuit Simulation ◽  
Detailed Circuit

Circuit Reliability Simulation

1995 ◽  
Vol 391 ◽  
Author(s):  
Chenming Hu
Keyword(s):  
Radiation Effects ◽  
Circuit Simulation ◽  
Physical Models ◽  
Design Stage ◽  
Circuit Reliability ◽  
Hot Electron ◽  
Simulation And Optimization ◽  
Design Changes ◽  
Hot Electron Effect ◽  
Detailed Circuit

AbstractIn designing a complex circuit, designers make a large number of circuit simulations, design changes and optimizations and can predict the circuit's performance reasonably accurately before committing it to silicon. It would be unthinkable to bypass detailed circuit simulation and optimization and rely on simple design rules and the testing of finished IC's to discover errors or to find out if the performance of the circuit meet specifications. Yet, this is basically the way IC reliability is treated today. A logical alternative is to predict circuit reliability at the circuit design stage through reliability simulation.Reliability simulator BERT is used to illustrate the physical models and approaches used to simulate the hot electron effect, oxide time-dependent breakdown, electromigration, bipolar transistor gain degradation, and radiation effects. The goal is to make circuit reliability simulation a part of the IC design process.

A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability

2021 ◽  
Vol 26 (6) ◽  
pp. 1-24
Author(s):  
Saranyu Chattopadhyay ◽  
Pranesh Santikellur ◽  
Rajat Subhra Chakraborty ◽  
Jimson Mathew ◽  
Marco Ottavi
Keyword(s):  
Lorenz System ◽  
High Reliability ◽  
Circuit Simulation ◽  
Design Framework ◽  
Chaotic Circuit ◽  
Hybrid Cmos ◽  
Function Design ◽  
Hardware Realization ◽  
Arbiter Puf ◽  
Detailed Circuit

Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

Nonlinear Circuit Simulation and Modeling

2018 ◽  
Author(s):  
José Carlos Pedro ◽  
David E. Root ◽  
Jianjun Xu ◽  
Luís Cótimos Nunes
Keyword(s):  
Circuit Simulation ◽  
Simulation And Modeling ◽  
Nonlinear Circuit

Application of AFP Nanoprobing Light-Induced Photovoltaic Current in the Failure Analysis

2017 ◽  
Author(s):  
C.Q. Chen ◽  
P.T. Ng ◽  
G.B. Ang ◽  
Francis Rivai ◽  
S.L. Ting ◽  
...  
Keyword(s):  
Image Analysis ◽  
Failure Analysis ◽  
Photovoltaic Effect ◽  
Electrical Characterization ◽  
Fault Isolation ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Current Image ◽  
Scaling Down ◽  
Detailed Circuit

Abstract As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.

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