Design of High Frequency and Energy Efficient 3D Frame Buffer on 40 nm FPGA

Author(s):  
Karandeep Kaur ◽  
Gurpinder Singh Ghuman ◽  
Tarandeep Kaur
2018 ◽  
Vol 5 (1) ◽  
pp. 31-40
Author(s):  
Md. Maidul Islam ◽  
Md. Mamun Ur Rashi

The DC-DC converter find a wide scope in industries, telecommunication sectors, power electronics area, etc. Nowadays bi-directional converters have a higher end over them since the energy from the load during regenerative braking is fed back to the source, thus obtaining energy efficient system. A single topology that can provide Buck-Boost operation with positive output having four quadrant operations is not available in the literature.  A common limitation of power coupling effect in some known multiple-input dc-dcconverters has been addressed in many kinds of literatures. In this paper, a new single topology of two quadrants DC-DC Sepic converter has been developed to provide four quadrant operation of a high- frequency dc-dc converter having one supply source and proper control of the converter. The combined topology has been analyzed and studied by spice simulation.


2018 ◽  
Vol 22 (12) ◽  
pp. 86-95 ◽  
Author(s):  
Alexander Livshits ◽  
◽  
Sergey Kargapoltsev ◽  
Nikolay Filippenko ◽  
Denis Butorin ◽  
...  

2021 ◽  
Vol 18 (3) ◽  
pp. 1-25
Author(s):  
Jose M. Rodriguez Borbon ◽  
Junjie Huang ◽  
Bryan M. Wong ◽  
Walid Najjar

QR decomposition is one of the most useful factorization kernels in modern numerical linear algebra algorithms. In particular, the decomposition of tall-and-skinny matrices (TSMs) has major applications in areas including scientific computing, machine learning, image processing, wireless networks, and numerical methods. Traditionally, CPUs and GPUs have achieved better throughput on these applications by using large cache hierarchies and compute cores running at a high frequency, leading to high power consumption. With the advent of heterogeneous platforms, however, FPGAs are emerging as a promising viable alternative. In this work, we propose a high-throughput FPGA-based engine that has a very high computational efficiency (ratio of achieved to peak throughput) compared to similar QR solvers running on FPGAs. Although comparable QR solvers achieve an efficiency of 36%, our design exhibits an efficiency of 54%. For TSMs, our experimental results show that our design can outperform highly optimized QR solvers running on CPUs and GPUs. For TSMs with more than 50K rows, our design outperforms the Intel MKL solver running on an Intel quad-core processor by a factor of 1.5×. For TSMs containing 256 columns or less, our design outperforms the NVIDIA CUBLAS solver running on a K40 GPU by a factor of 3.0×. In addition to being fast, our design is energy efficient—competing platforms execute up to 0.6 GFLOPS/Joule, whereas our design executes more than 1.0 GFLOPS/Joule.


2021 ◽  
pp. 128548
Author(s):  
Muaaz Abdul Hadi ◽  
Markus Brillinger ◽  
Marcel Wuwer ◽  
Johannes Schmid ◽  
Stefan Trabesinger ◽  
...  

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