scholarly journals Injection-Locked Clocking: A New GHz Clock Distribution Scheme

2006 ◽  
Author(s):  
Lin Zhang ◽  
Berkehan Ciftcioglu ◽  
Michael Huang ◽  
Hui Wu
Keyword(s):  
Clock Distribution ◽  
Distribution Scheme

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

2008 ◽  
Vol 16 (9) ◽  
pp. 1251-1256 ◽  
Author(s):  
Lin Zhang ◽  
A. Carpenter ◽  
B. Ciftcioglu ◽  
A. Garg ◽  
M. Huang ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Clock Distribution ◽  
Distribution Scheme

A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL

2010 ◽  
Vol 57 (2) ◽  
pp. 589-594 ◽  
Author(s):  
Jie Wu ◽  
Yichao Ma ◽  
Jie Zhang ◽  
Mingpu Xie
Keyword(s):  
Clock Distribution ◽  
Distribution Scheme ◽  
Low Jitter

Clock distribution scheme for high-speed DRAM

2002 ◽  
Vol 38 (13) ◽  
pp. 626
Author(s):  
J. Kook ◽  
J.-K. Wee ◽  
G. Moon ◽  
S. Lee
Keyword(s):  
High Speed ◽  
Clock Distribution ◽  
Distribution Scheme

scholarly journals A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems

VLSI Design ◽  
1995 ◽  
Vol 3 (1) ◽  
pp. 81-92 ◽  
Author(s):  
Ahmed El-Amawy ◽  
Umasankar Maheshwar
Keyword(s):  
Comparative Study ◽  
Binary Tree ◽  
Clock Distribution ◽  
Clock Skew ◽  
Vlsi Layout ◽  
Tree Network ◽  
Threshold Size ◽  
Area Efficiency ◽  
Distribution Scheme ◽  
Tree Approach

Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a VLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. The H-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root. Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevant parameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, node costs and area efficiency as the basis for comparison. We show that for each BaC network, there is a certain threshold size after which it outperforms the corresponding tree network in terms of skew. We also show that except for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network is large. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matter how large the network is.

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