A cached frame buffer system for object-space parallel processing systems

Proceedings Computer Graphics International ◽

10.1109/cgi.1997.601296 ◽

2002 ◽

Cited By ~ 1

Author(s):

H. Kobayashi ◽

T. Maeda ◽

H. Yamauchi ◽

T. Nakamura

Keyword(s):

Parallel Processing ◽

Buffer System ◽

Object Space ◽

Frame Buffer

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A frame buffer system with enhanced functionality

ACM SIGGRAPH Computer Graphics ◽

10.1145/965161.806790 ◽

1981 ◽

Vol 15 (3) ◽

pp. 63-69 ◽

Cited By ~ 2

Author(s):

F. C. Crow ◽

M. W. Howard

Keyword(s):

Buffer System ◽

Frame Buffer

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Parallel processing of an object space for image synthesis using ray tracing

The Visual Computer ◽

10.1007/bf02153647 ◽

1987 ◽

Vol 3 (1) ◽

pp. 13-22 ◽

Cited By ~ 20

Author(s):

Hiroaki Kobayashi ◽

Tadao Nakamura ◽

Yoshiharu Shigei

Keyword(s):

Parallel Processing ◽

Ray Tracing ◽

Image Synthesis ◽

Object Space

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AN EFFICIENT MEMORY ADDRESS CONVERTER FOR SoC-BASED 3D GRAPHICS SYSTEM

Journal of Circuits System and Computers ◽

10.1142/s0218126605002647 ◽

2005 ◽

Vol 14 (04) ◽

pp. 861-875

Author(s):

JOUNG-YOUN KIM ◽

LEE-SUP KIM

Keyword(s):

Pattern Analysis ◽

System Optimization ◽

Buffer System ◽

3D Graphics ◽

Dynamic Power Management ◽

Access Pattern ◽

Frame Buffer ◽

Memory Address ◽

Memory Modules ◽

Efficient Memory

In this paper, we propose an architecture level analysis of the frame buffer access pattern of the recent 3D graphics accelerators that utilize multiple pipelined rendering engines. Based on this analysis, we propose an energy efficient memory address converter for an SoC-based 3D graphics system with an SDRAM frame buffer. About 30% of energy reduction and 20% of runtime reduction is obtained with the address converter. With dynamic power management feature of SDRAM, the energy gains increase to about 50%. The energy and runtime gains are generated by an access pattern analysis based division and assignment of frame buffer onto multiple memory modules. With this proposed access pattern analysis, a frame buffer system optimization of an IP-based 3D graphics accelerator can be performed at early architecture design level.

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