On computation of bit error probability in communication systems

The standard Monte Carlo estimations of rare events probabilities suffer from too much computational time. To make estimations faster, kernel-based estimators proved to be more efficient for binary systems whilst appearing to be more suitable in situations where the probability density function of the samples is unknown. We propose a kernel-based Bit Error Probability (BEP) estimator for coded M-ary Quadrature Amplitude Modulation (QAM) systems. We defined soft real bits upon which an Epanechnikov kernel-based estimator is designed. Simulation results showed, compared to the standard Monte Carlo simulation technique, accurate, reliable and efficient BEP estimates for 4-QAM and 16-QAM symbols transmissions over the additive white Gaussian noise channel and over a frequency-selective Rayleigh fading channel. Les estimations de probabilités d'événements rares par la méthode de Monte Carlo classique souffrent de trop de temps de calculs. Des estimateurs à noyau se sont montrés plus efficaces sur des systèmes binaires en même temps qu'ils paraissent mieux adaptés aux situations où la fonction de densité de probabilité est inconnue. Nous proposons un estimateur de Probabilité d'Erreur Bit (PEB) à noyau pour les systèmes M-aires codés de Modulations d'Amplitude en Quadrature (MAQ). Nous avons défini des bits souples à valeurs réelles à partir desquels un estimateur à noyau d'Epanechnikov est conçu. Les simulations ont montré, par rapport à la méthode Monte Carlo, des estimées de PEB précises, fiables et efficaces pour des transmissions MAQ-4 et MAQ-16 sur canaux à bruit additif blanc Gaussien et à évanouïssements de Rayleigh sélectif en fréquence.

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An Efficient Weighted Bit-Flipping Algorithm for Decoding LDPC Codes Based on Log-Likelihood Ratio of Bit Error Probability

IEICE Transactions on Communications ◽

10.1587/transcom.2016ebp3376 ◽

2017 ◽

Vol E100.B (12) ◽

pp. 2095-2103 ◽

Cited By ~ 1

Author(s):

Tso-Cho CHEN ◽

Erl-Huei LU ◽

Chia-Jung LI ◽

Kuo-Tsang HUANG

Keyword(s):

Likelihood Ratio ◽

Error Probability ◽

Ldpc Codes ◽

Bit Error Probability ◽

Log Likelihood ◽

Log Likelihood Ratio

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Ratio-based multi-level resistive memory cells

Scientific Reports ◽

10.1038/s41598-020-80121-7 ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

Miguel Angel Lastras-Montaño ◽

Osvaldo Del Pozo-Zamudio ◽

Lev Glebsky ◽

Meiran Zhao ◽

Huaqiang Wu ◽

...

Keyword(s):

Error Probability ◽

Resistance Switching ◽

Closed Form Expression ◽

Memory Cells ◽

Resistive Memory ◽

Worst Case ◽

Information Encoding ◽

Bit Error Probability ◽

Multi Level ◽

Switching Devices

AbstractRatio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to $$x^2$$ x 2 at the best case and $$x^{\sqrt{2}}$$ x 2 at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10$$\times$$ × , while achieving the same bit error probability.

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