A low complexity algorithm for sampling clock-offset compensation in low power WPAN receivers

2016 ◽  
Author(s):  
Sujit Jos ◽  
Kiran Bynam ◽  
Chandrashekhar Thejaswi P S ◽  
Ashutosh Deepak Gore ◽  
Young-Jun Hong ◽  
...  
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Offset Compensation ◽  
Clock Offset ◽  
Complexity Algorithm

A Low Complexity Algorithm to Improve Data Rates in LTE MBMS Systems.

2015 ◽  
Vol 4 (1) ◽  
pp. 25-29
Author(s):  
Vidyapogula Naveen ◽  
◽  
S. Thulasi Prasad ◽  
Keyword(s):  
Low Complexity ◽  
Data Rates ◽  
Complexity Algorithm

scholarly journals A high throughput architecture for a low complexity soft-output demapping algorithm

2015 ◽  
Vol 13 ◽  
pp. 73-80 ◽  
Author(s):  
I. Ali ◽  
U. Wasenmüller ◽  
N. Wehn
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Turbo Code ◽  
Low Complexity ◽  
Implementation Cost ◽  
Qam Modulation ◽  
Iterative Systems ◽  
Very High ◽  
Complexity Algorithm ◽  
Hardware Performance

Abstract. Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

scholarly journals A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

2019 ◽  
Vol 17 ◽  
pp. 145-150
Author(s):  
Markus Scholl ◽  
Ralf Wunderlich ◽  
Stefan Heinen
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Calibration Method ◽  
Low Complexity ◽  
Frequency Stability ◽  
Wireless Communication Systems ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Digital Frequency ◽  
Frequency Calibration

Abstract. This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems. This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its send- and receive-state to achieve frequency stability over process variation and temperature drifts. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power oscillator's by utilizing non-linear segmented feedback levels. In measurements the proposed calibration method improves the frequency stability of an ultra-low-power 32 kHz oscillator from 53 to 10 ppm ∘C−1 over a wide temperature range for temperature drifts of less than 1 ∘C s−1 with an estimated power consumption of 185 nW while coping with relocking periods of 7 ms.

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

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