Reliability evaluation of multivalued logic circuits via probabilistic transfer matrices

2012 ◽  
Author(s):  
A. Abbasinasab ◽  
S. N. Yanushkevich
Keyword(s):  
Reliability Evaluation ◽  
Logic Circuits ◽  
Multivalued Logic ◽  
Transfer Matrices

Signal probability for reliability evaluation of logic circuits

2008 ◽  
Vol 48 (8-9) ◽  
pp. 1586-1591 ◽  
Author(s):  
Denis Teixeira Franco ◽  
Maí Correia Vasconcelos ◽  
Lirida Naviner ◽  
Jean-François Naviner
Keyword(s):  
Reliability Evaluation ◽  
Logic Circuits ◽  
Signal Probability

scholarly journals Probabilistic transfer matrices in symbolic reliability analysis of logic circuits

2008 ◽  
Vol 13 (1) ◽  
pp. 1-35 ◽  
Author(s):  
Smita Krishnaswamy ◽  
George F. Viamontes ◽  
Igor L. Markov ◽  
John P. Hayes
Keyword(s):  
Reliability Analysis ◽  
Logic Circuits ◽  
Transfer Matrices

Analysis and applications of new I2L multivalued logic circuits

1982 ◽  
Vol 65 (1) ◽  
pp. 91-98
Author(s):  
Kazutaka Taniguchi ◽  
Takahiro Inoue ◽  
Fumio Ueno
Keyword(s):  
Logic Circuits ◽  
Multivalued Logic

scholarly journals Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices

2005 ◽  
Author(s):  
S. Krishnaswamy ◽  
G.F. Viamontes ◽  
I.L. Markov ◽  
J.P. Hayes
Keyword(s):  
Reliability Evaluation ◽  
Transfer Matrices

scholarly journals Reliability evaluation of logic circuits based on transient faults propagation metrics

2017 ◽  
Vol 14 (7) ◽  
pp. 20170128-20170128 ◽  
Author(s):  
Shuo Cai ◽  
Fei Yu ◽  
Weizheng Wang ◽  
Tieqiao Liu ◽  
Peng Liu ◽  
...  
Keyword(s):  
Reliability Evaluation ◽  
Logic Circuits ◽  
Transient Faults

SPLM: A Flexible and Accurate Reliability Assessment Model for Logic Circuits

2018 ◽  
Vol 28 (02) ◽  
pp. 1950032
Author(s):  
Xingjian Xu ◽  
Tian Ban ◽  
Yuehua Li
Keyword(s):  
Computational Models ◽  
Reliability Assessment ◽  
Reliability Evaluation ◽  
Logic Circuits ◽  
Research Field ◽  
Assessment Model ◽  
Signal Probability ◽  
Design Constraints ◽  
Proposed Model ◽  
Cascade Structure

Reliability evaluation by using probabilistic computational models has become an important research field in modern digital designs. Based on the profound understanding of different reliability evaluation methods, this paper proposes a universal model for signal probability and reliability analysis of logic circuits. The proposed Signal Probability Level Matrix (SPLM) provides us with the reliability and signal probability of the entire circuit as well as individual outputs. We can deal with SPLM very flexibly depending on different applications and design constraints. The accuracy and efficiency of the proposed model have been proved and verified by representative circuits in literatures. Furthermore, the proposed model is particularly useful in reliability assessment in cascade-structure circuits such as ripple carry adders.

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