In this paper, simulation study has been carried out on two inputs logic NAND transistor circuits with four different logic families, namely (i) nano-CMOS NAND gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NAND gate, (iii) resistive loaded nano-MOSFET NAND gate, and (iv) pseudo nano-MOSFET NAND gate. The simulation tool used is WinSpice. All the n-type and p-type nano-MOSFETs have channel length (L) 10 nm with width (W) 125 nm or 250 nm, depending on type of logic families. The problem with downscaling of nano-MOSFET is the implementation of low power high speed nano-MOSFET transistor circuit. Simulated timing diagrams for input and output waveforms showed correct logical NAND gate operations for all four logic families. Transient analysis on nano-MOSFET loaded n-type nano-MOSFET NAND gate shows that theoretical modeling calculation of rise time (tr), fall time (tf) and maximum operating frequency (fmax) are reasonably matched simulated output result of WinSpice. All the logic family circuits studied shown reduction in dynamic power when MOSFET is downscaled to nanometer regime.
Temporal Modalities for Concisely Capturing Timing Diagrams