Multiplier-less based architecture for variable-length FFT hardware implementation

2012 ◽  
Author(s):  
Nguyen Hung Cuong ◽  
Nguyen Tung Lam ◽  
Nguyen Duc Minh
Keyword(s):  
Hardware Implementation ◽  
Variable Length

scholarly journals 4 Maximum Likelihood Decoder for Variable Length Codes

2012 ◽  
Vol 1 (1) ◽  
pp. 5
Author(s):  
Syed Misbahuddin ◽  
Mohammed Talal Simsim
Keyword(s):  
Error Propagation ◽  
Hardware Implementation ◽  
Variable Length ◽  
Digital Information ◽  
Description Language ◽  
Probability Of Occurrence ◽  
Symmetric Channel ◽  
Short Period ◽  
Hardware Description ◽  
Variable Length Codes

Variable Length Codes (VLC) are used to transfer same amount of digital information in relatively short period of time. In variable length coding, the characters with higher probability of occurrence are assigned shorter bits sequence and the characters with less probability of occurrence are assigned relatively longer bits sequence. However, due to variable length nature of codes, the decoding circuitry at the receiving end loses the synchronization due to single or multiple bit inversions. This typically happens when data is transmitted through a Binary Symmetric Channel (BSC). This paper investigates synchronizing scheme to control the error propagation due to single or multiple bit inversions through BSC. The hardware implementation of the proposed algorithm has been presented using a hardware description language. The functional level simulation of the implementation is discussed to test the proposed algorithm.

scholarly journals 4 Maximum Likelihood Decoder for Variable Length Codes

2012 ◽  
Vol 2 (1) ◽  
pp. 5
Author(s):  
Syed Misbahuddin ◽  
Mohammed Talal Simsim
Keyword(s):  
Error Propagation ◽  
Hardware Implementation ◽  
Variable Length ◽  
Digital Information ◽  
Description Language ◽  
Probability Of Occurrence ◽  
Symmetric Channel ◽  
Short Period ◽  
Hardware Description ◽  
Variable Length Codes

Variable Length Codes (VLC) are used to transfer same amount of digital information in relatively short period of time. In variable length coding, the characters with higher probability of occurrence are assigned shorter bits sequence and the characters with less probability of occurrence are assigned relatively longer bits sequence. However, due to variable length nature of codes, the decoding circuitry at the receiving end loses the synchronization due to single or multiple bit inversions. This typically happens when data is transmitted through a Binary Symmetric Channel (BSC). This paper investigates synchronizing scheme to control the error propagation due to single or multiple bit inversions through BSC. The hardware implementation of the proposed algorithm has been presented using a hardware description language. The functional level simulation of the implementation is discussed to test the proposed algorithm.

An Improvement of Rate-Distortion Optimized Quantization Process and its Hardware Implementation

2015 ◽  
Vol 135 (11) ◽  
pp. 1299-1306
Author(s):  
Genki Moriguchi ◽  
Takashi Kambe ◽  
Gen Fujita ◽  
Hajime Sawano
Keyword(s):  
Hardware Implementation ◽  
Rate Distortion

Simulation and Hardware Implementation of Grid Connected Solar Charge Controller with MPPT

2015 ◽  
Vol 1 (3) ◽  
pp. 4 ◽  
Author(s):  
Prof.Vipul Patel ◽  
Prof. Sanjay Patel ◽  
Nikunj Patel ◽  
Prof.Sanjay Prajapati
Keyword(s):  
Hardware Implementation

Performance enhancement of Echo Cancellation Using a Combination of Partial Update ( PU) Methods and New Variable Length LMS (NVLLMS) Algorithm

2018 ◽  
Vol 24 (5) ◽  
pp. 66
Author(s):  
Thamer M. Jamel ◽  
Faez Fawzi Hammood
Keyword(s):  
Mean Square Error ◽  
Return Loss ◽  
Performance Enhancement ◽  
Variable Length ◽  
Echo Cancellation ◽  
Convergence Time ◽  
Length Variation ◽  
Mean Square ◽  
Step Size ◽  
Echo Return Loss Enhancement

In this paper, several combination algorithms between Partial Update LMS (PU LMS) methods and previously proposed algorithm (New Variable Length LMS (NVLLMS)) have been developed. Then, the new sets of proposed algorithms were applied to an Acoustic Echo Cancellation system (AEC) in order to decrease the filter coefficients, decrease the convergence time, and enhance its performance in terms of Mean Square Error (MSE) and Echo Return Loss Enhancement (ERLE). These proposed algorithms will use the Echo Return Loss Enhancement (ERLE) to control the operation of filter's coefficient length variation. In addition, the time-varying step size is used.The total number of coefficients required was reduced by about 18% , 10% , 6%, and 16% using Periodic, Sequential, Stochastic, and M-max PU NVLLMS algorithms respectively, compared to that used by a full update method which  is very important, especially in the application of mobile communication since the power consumption must be considered. In addition, the average ERLE and average Mean Square Error (MSE) for M-max PU NVLLMS are better than other proposed algorithms.  

A Test Data Compression Scheme Based on Mixed Fixed and Variable Length Coding

2009 ◽  
Vol 31 (10) ◽  
pp. 1826-1834 ◽  
Author(s):  
Wen-Fa ZHAN ◽  
Hua-Guo LIANG ◽  
Feng SHI ◽  
Zheng-Feng HUANG
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Variable Length ◽  
Test Data Compression ◽  
Compression Scheme ◽  
Variable Length Coding
Sign in / Sign up

Export Citation Format

Share Document