A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration

2017 ◽  
Author(s):  
Seiya Ogido ◽  
Chikatoshi Yamada ◽  
Kei Miyagi ◽  
Shuichi Ichikawa
Keyword(s):  
Fault Tolerant ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Fault Tolerant System

scholarly journals Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption

2011 ◽  
Vol 2011 ◽  
pp. 1-25 ◽  
Author(s):  
R. Al-Haddad ◽  
R. Oreifej ◽  
R. A. Ashraf ◽  
R. F. DeMara
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Repair Time ◽  
Self Healing ◽  
Partial Reconfiguration ◽  
Organic System ◽  
Dynamic Partial Reconfiguration ◽  
Novel Approach ◽  
Field Programmable ◽  
Sobel Edge Detection

As reconfigurable devices' capacities and the complexity of applications that use them increase, the need forself-relianceof deployed systems becomes increasingly prominent. Organic computing paradigms have been proposed for fault-tolerant systems because they promote behaviors that allow complex digital systems to adapt and survive in demanding environments. In this paper, we develop asustainable modular adaptive redundancy technique (SMART)composed of a two-layered organic system. The hardware layer is implemented on a XilinxVirtex-4Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach calledreconfigurable adaptive redundancy system (RARS). The software layer supervises the organic activities on the FPGA and extends the self-healing capabilities through application-independent, intrinsic, and evolutionary repair techniques that leverage the benefits of dynamic partial reconfiguration (PR). SMART was evaluated using a Sobel edge-detection application and was shown to tolerate stressful sequences of injected transient and permanent faults while reducing dynamic power consumption by 30% compared to conventionaltriple modular redundancy (TMR)techniques, with nominal impact on the fault-tolerance capabilities. Moreover, PR is employed to keep the system on line while under repair and also to reduce repair time. Experiments have shown a 27.48% decrease in repair time when PR is employed compared to the full bitstream configuration case.

Fault-Tolerant Strategy for Real-Time System Based on Evolvable Hardware

2017 ◽  
Vol 26 (07) ◽  
pp. 1750111 ◽  
Author(s):  
Jie Wang ◽  
Jiwei Liu
Keyword(s):  
Real Time ◽  
Recovery Time ◽  
Fault Tolerant ◽  
Fault Tree Analysis ◽  
Repair Process ◽  
Evolvable Hardware ◽  
Target System ◽  
Time System ◽  
Real Time System ◽  
Fault Tolerant System

The evolvable hardware (EHW) is widely used in the design of fault-tolerant system. Fault-tolerant system is really a real-time system, and the recovery time is necessary in fault detection and recovery. However, when applying EHW, real-time characteristic is usually ignored. In this paper, a fault-tolerant strategy based on EHW is proposed. The recovery time, predicted by the fault tree analysis (FTA), is considered as a constraint condition. A configuration library is set up in the design phase to accelerate the repair process of the anticipated faults. An evolvable algorithm (EA) based on similarity is applied to evolve the repair circuit for the unanticipated faults. When the library reaches the upper, the target system is reconfigured by the EA-repair technology. Extensive experiments are conducted to show that our method can improve the fault-tolerance of the system while satisfying the real-time requirement on FPGA platform. In a long run system, our method can keep a higher fault recovery rate.

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