Hardware Implementation of Prearranged Tables Based Modular Inversion

2011 ◽  
Author(s):  
Tsutomu Ishida ◽  
Yoshio Yoshioka ◽  
Tomoyuki Nagase
Keyword(s):  
Hardware Implementation ◽  
Modular Inversion

scholarly journals An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

2019 ◽  
Vol 8 (9) ◽  
pp. 827-832
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Hardware Implementation ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Inversion Algorithm ◽  
Prime Field ◽  
Modular Inversion ◽  
Reduction In Area ◽  
Computing Speed

The modular inversion operation is an essential hardware design for computing speed when we use it in cryptography applications. Through this work, we present a FSM based design methodology to achieve speed, area and high-performance modular binary inversion algorithm over 256-bit prime field. The proposed architecture implemented using Xilinx Virtex-7 FPGA device, it achieves 37% reduction in area-delay product and 15% and 16% of improvement in speed and throughput respectively, when compared with existing designs. Also, ASIC based implementation is done using TSMC 65nm CMOS technology, the synthesis results achieved the maximum operating clock frequency is 833 MHz and throughput of 626Mbps, which makes it suitable for speed-critical cryptoapplications.

An Improvement of Rate-Distortion Optimized Quantization Process and its Hardware Implementation

2015 ◽  
Vol 135 (11) ◽  
pp. 1299-1306
Author(s):  
Genki Moriguchi ◽  
Takashi Kambe ◽  
Gen Fujita ◽  
Hajime Sawano
Keyword(s):  
Hardware Implementation ◽  
Rate Distortion

Simulation and Hardware Implementation of Grid Connected Solar Charge Controller with MPPT

2015 ◽  
Vol 1 (3) ◽  
pp. 4 ◽  
Author(s):  
Prof.Vipul Patel ◽  
Prof. Sanjay Patel ◽  
Nikunj Patel ◽  
Prof.Sanjay Prajapati
Keyword(s):  
Hardware Implementation

scholarly journals Hardware implementation of radial-basis neural networks with Gaussian activation functions on FPGA

2021 ◽  
Author(s):  
Volodymyr Shymkovych ◽  
Sergii Telenyk ◽  
Petro Kravets
Keyword(s):  
Neural Networks ◽  
Hardware Implementation ◽  
Gaussian Function ◽  
Activation Function ◽  
Rbf Neural Networks ◽  
Activation Functions ◽  
Rbf Network ◽  
Combination Scheme ◽  
Radial Basis ◽  
Hidden Layer

AbstractThis article introduces a method for realizing the Gaussian activation function of radial-basis (RBF) neural networks with their hardware implementation on field-programmable gaits area (FPGAs). The results of modeling of the Gaussian function on FPGA chips of different families have been presented. RBF neural networks of various topologies have been synthesized and investigated. The hardware component implemented by this algorithm is an RBF neural network with four neurons of the latent layer and one neuron with a sigmoid activation function on an FPGA using 16-bit numbers with a fixed point, which took 1193 logic matrix gate (LUTs—LookUpTable). Each hidden layer neuron of the RBF network is designed on an FPGA as a separate computing unit. The speed as a total delay of the combination scheme of the block RBF network was 101.579 ns. The implementation of the Gaussian activation functions of the hidden layer of the RBF network occupies 106 LUTs, and the speed of the Gaussian activation functions is 29.33 ns. The absolute error is ± 0.005. The Spartan 3 family of chips for modeling has been used to get these results. Modeling on chips of other series has been also introduced in the article. RBF neural networks of various topologies have been synthesized and investigated. Hardware implementation of RBF neural networks with such speed allows them to be used in real-time control systems for high-speed objects.

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