Receiver Chip in 0.6µm BiCMOS with AGC and LVDS Output Driver

2017 ◽  
Author(s):  
Bernhard Goll ◽  
Robert Swoboda ◽  
Horst Zimmermann
Keyword(s):  
Output Driver

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

2022 ◽  
Vol 17 (01) ◽  
pp. C01040
Author(s):  
C. Zhao ◽  
D. Guo ◽  
Q. Chen ◽  
N. Fang ◽  
Y. Gan ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Test Results ◽  
Eye Diagram ◽  
Optical Links ◽  
Optical Module ◽  
Active Feedback ◽  
High Bandwidth ◽  
Output Driver ◽  
Very High

Abstract This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

On Small Scale LNG Concepts

2021 ◽  
Author(s):  
Rainer Kurz ◽  
Min Ji ◽  
Griffin Beck ◽  
Timothy C. Allison
Keyword(s):  
Gas Turbines ◽  
Operating Conditions ◽  
Process Efficiency ◽  
Small Scale ◽  
Control Methods ◽  
Electric Drives ◽  
Output Driver ◽  
The Relationship ◽  
Equipment Performance

Abstract The different economics of small scale LNG plants put more emphasis on capital expenses over process efficiency, and thus favors simpler refrigeration cycles. We typically find reverse Brayton cycles, or SMR (Single mixed refrigerant) cycles. These cycles have specific requirements to the compression equipment, and typically have smaller drivers, either electric drives or gas turbines. The relationship between output, driver size, and process preferences is explained. The type of compressors, and expanders needed are discussed, together with thoughts and the driver preferences. This includes the different control methods that can be used, both for the cycle adaptation, as well as the related control of the compressors, expanders, valves and drivers. Equipment performance maps are created to highlight the required different operating conditions. This result allows for subsequent optimization discussions.

A One-Cycle Lock Time Slew-Rate-Controlled Output Driver

2007 ◽  
Author(s):  
Young-Ho Kwak ◽  
Inhwa Jung ◽  
Hyung-Dong Lee ◽  
Young-Jung Choi ◽  
Yogendera Kumar ◽  
...  
Keyword(s):  
Slew Rate ◽  
Rate Controlled ◽  
Output Driver

Research and Development of Automatic Control System on Material Split Packing and Packaging Integrated Machine

2014 ◽  
Vol 533 ◽  
pp. 294-297
Author(s):  
Kai Yang ◽  
Zhong Shen Li ◽  
Lei Zhang
Keyword(s):  
Control System ◽  
High Speed ◽  
High Reliability ◽  
Automatic Measurement ◽  
Power Module ◽  
Memory Module ◽  
Machine Interface ◽  
Output Driver ◽  
And Control ◽  
Measurement And Control

In order to meet the high speed, high precision, high reliability of the packaging machine, a novel control system is provided. In the hardware, the main circuits consisted of main processor module, memory module, temperature measurement and control module, input signal detection module, material split packing module, output driver module, human-machine interface module, system monitor module, power module and JTAG debug module, etc. In the software, the multi-tasking operating system μC/OS-Ⅱ and the graphical user interface μC/GUI were successfully transplanted into LPC2478. Then an experimental platform was established. And many control tasks, including automatic measurement, making bags, loading, transferring, pumping vacuum, sealing and data display, were automatically and continuously executed on the platform. Finally the results show: the machine can package 30 packets (5 g per packet) in a minute; the packaging errors ≤ 0.2 g; the packaging qualified rates ≥ 93%. In conclusion, the system performance is good.

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