A Soft Error Resilient Low Leakage SRAM Cell Design

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.373-375.1607 ◽

2013 ◽

Vol 373-375 ◽

pp. 1607-1611

Author(s):

Hong Gang Zhou ◽

Shou Biao Tan ◽

Qiang Song ◽

Chun Yu Peng

Keyword(s):

Error Correction ◽

Low Voltage ◽

Cmos Technology ◽

Soft Error ◽

Error Correction Codes ◽

Cell Design ◽

Low Voltage Operation ◽

Sram Cell ◽

Simulation Results ◽

Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

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A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability

Wireless Personal Communications ◽

10.1007/s11277-016-3788-5 ◽

2016 ◽

Vol 94 (4) ◽

pp. 3513-3529 ◽

Cited By ~ 5

Author(s):

Rohit Lorenzo ◽

Saurabh Chaudhury

Keyword(s):

High Speed ◽

Cell Design ◽

Low Leakage ◽

Sram Cell ◽

Improved Stability ◽

Body Bias

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Process Variability Aware Low Leakage Reliable Nano Scale Double-Gate-FinFET SRAM Cell Design Technique

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2015.1843 ◽

2015 ◽

Vol 10 (6) ◽

pp. 810-817 ◽

Cited By ~ 4

Author(s):

Saurabh Khandelwal ◽

Vishal Gupta ◽

Balwinder Raj ◽

R. D. Gupta

Keyword(s):

Double Gate ◽

Cell Design ◽

Design Technique ◽

Process Variability ◽

Nano Scale ◽

Low Leakage ◽

Sram Cell

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Soft Error-Resilient RHBD16T SRAM Cell in 32nm Technology

Advances in Computer and Electrical Engineering - Innovative Applications of Nanowires for Circuit Design ◽

10.4018/978-1-7998-6467-7.ch008 ◽

2021 ◽

pp. 171-188

Author(s):

Gaurav Kaushal ◽

Balamurugan Murgan ◽

Manisha Pattanaik ◽

Chinnapurapu Naga Raghuram ◽

Surendra Singh Rathod

Keyword(s):

Random Access ◽

Error Rates ◽

Soft Error ◽

Radiation Environment ◽

Static Random Access Memory ◽

Single Node ◽

Error Resilient ◽

Sram Cell ◽

Radiation Hardened ◽

Simulation Results

Radiation environment generates high soft error rates in conventional SRAM. To overcome this issue, several radiation hardened by design SRAM circuits (12TRHBD, 13TRHBD, DICE, etc.) have been developed. Although many of the radiation hardened SRAM cells are there, all the circuits mainly concern a single node upset only. In this chapter, 16T radiation hardened static random-access memory bit cell is designed and verified for a single node and multi-node upset. RHBD 16T bit cell is designed with SAED-PDK 32nm technology and compared with recently reported RHBD 12T and has a 99% improvement in recovery rate. Simulation results show that RHBD 16T is more resilient to a single node and multi-node upset. This shows that the proposed RHBD16T cell is highly tolerant against radiation strikes.

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Data-Retention Sleep Transistor CNTFET SRAM Cell Design at 32nm Technology for Low-Leakage

Mobile Communication and Power Engineering - Communications in Computer and Information Science ◽

10.1007/978-3-642-35864-7_54 ◽

2013 ◽

pp. 362-368

Author(s):

S. Rajendra Prasad ◽

B. K. Madhavi ◽

K. Lal Kishore

Keyword(s):

Cell Design ◽

Data Retention ◽

Low Leakage ◽

Sram Cell

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A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

Advances in Radio Science ◽

10.5194/ars-3-355-2005 ◽

2005 ◽

Vol 3 ◽

pp. 355-358

Author(s):

A. Schmitz ◽

R. Tielert

Keyword(s):

Supply Voltage ◽

Logic Gate ◽

Deep Submicron ◽

Soft Error ◽

Sleep Mode ◽

Leakage Currents ◽

Low Leakage ◽

Sram Cell ◽

Local Supply ◽

Standby Mode

Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

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