An on-chip dynamically recalibrated delay line for embedded self-timed systems

2002 ◽  
Author(s):  
G. Taylor ◽  
S. Moore ◽  
S. Wilcox ◽  
P. Robinson
Keyword(s):  
Delay Line ◽  
Timed Systems ◽  
On Chip

System Performances of On-Chip Silicon Microring Delay Line for RZ, CSRZ, RZ-DB and RZ-AMI Signals

2008 ◽  
Vol 26 (23) ◽  
pp. 3744-3751 ◽  
Author(s):  
Qiang Li ◽  
Fangfei Liu ◽  
Ziyang Zhang ◽  
Min Qiu ◽  
Yikai Su
Keyword(s):  
Delay Line ◽  
On Chip

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

2021 ◽  
pp. 2150146
Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Delay Model ◽  
Analysis And Design ◽  
True Time Delay ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Relative Delay ◽  
True Time ◽  
On Chip

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

Gigahertz tuning of on-chip RF photonic delay line

2017 ◽  
Author(s):  
Yang Liu ◽  
Amol Choudhary ◽  
David Marpaung ◽  
Benjamin J. Eggleton
Keyword(s):  
Delay Line ◽  
On Chip

Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements

2013 ◽  
Vol 596 ◽  
pp. 176-180
Author(s):  
Kiichi Niitsu ◽  
Kazunori Sakuma ◽  
Naohiro Harigai ◽  
Daiki Hirabayashi ◽  
Nobukazu Takai ◽  
...  
Keyword(s):  
Design Methodology ◽  
Thermal Noise ◽  
Delay Line ◽  
Cmos Technology ◽  
High Accuracy ◽  
Delay Lines ◽  
Spice Simulation ◽  
Simulation Results ◽  
On Chip

This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter generation.

A POWER AND AREA EFFICIENT 65 nm CMOS DELAY-LINE ADC FOR ON-CHIP VOLTAGE SENSING

2013 ◽  
Vol 22 (09) ◽  
pp. 1340014 ◽  
Author(s):  
SIDA AMY SHEN ◽  
SHUANG XIE ◽  
WAI TUNG NG
Keyword(s):  
Power Management ◽  
Delay Line ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Voltage Sensing ◽  
Circuit Performance ◽  
Analog To Digital ◽  
Dynamic Voltage ◽  
On Chip ◽  
Area Efficient

This paper presents a 4-bit windowed delay-line analog-to-digital converter (ADC) implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm2. With a sampling rate of 4 MHz, the ADC consumes 14 μW with an ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.

scholarly journals Error-free continuously-tunable delay at 10 Gbit/s in a reconfigurable on-chip delay-line

2008 ◽  
Vol 16 (12) ◽  
pp. 8395 ◽  
Author(s):  
Francesco Morichetti ◽  
Andrea Melloni ◽  
Carlo Ferrari ◽  
Mario Martinelli
Keyword(s):  
Delay Line ◽  
On Chip
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