A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

2002 ◽  
Author(s):  
G. Matsubara ◽  
N. Ide
Keyword(s):  
Low Power ◽  
Square Root

Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation

2019 ◽  
Vol 68 (11) ◽  
pp. 1635-1646 ◽  
Author(s):  
Honglan Jiang ◽  
Leibo Liu ◽  
Fabrizio Lombardi ◽  
Jie Han
Keyword(s):  
Low Power ◽  
Square Root ◽  
Adaptive Approximation

Proposed low power, high speed adder-based 65-nm Square root circuit

2011 ◽  
Vol 42 (2) ◽  
pp. 445-451 ◽  
Author(s):  
C. Senthilpari ◽  
Zuraida Irina Mohamad ◽  
S. Kavitha
Keyword(s):  
Low Power ◽  
High Speed ◽  
Square Root

scholarly journals Low Power Square Root Carry Select Adder Using AVLS-TSPC-Based D Flip-Flop

2021 ◽  
Author(s):  
Premananda Belegahalli Siddaiah ◽  
◽  
Nikhil Kiran Jayanthi ◽  
Samana Hanumanth Managoli ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Square Root ◽  
Flip Flop ◽  
Carry Select Adder
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