A 6.5-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180nm CMOS Technology

2006 ◽  
Author(s):  
Takahiro Ishii ◽  
Hiroyuki Ito ◽  
Makoto Kimura ◽  
Kenichi Okada ◽  
Kazuya Masu
Keyword(s):  
Transmission Line ◽  
Cmos Technology ◽  
Low Latency ◽  
Differential Transmission ◽  
On Chip

A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology

2013 ◽  
Author(s):  
Gautam R. Gangasani ◽  
John F. Bulzacchelli ◽  
Troy Beukema ◽  
Chun-Ming Hsu ◽  
William Kelly ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Latency ◽  
On Chip ◽  
Soi Cmos

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

2014 ◽  
Vol 49 (11) ◽  
pp. 2474-2489 ◽  
Author(s):  
Gautam R. Gangasani ◽  
Chun-Ming Hsu ◽  
John F. Bulzacchelli ◽  
Troy Beukema ◽  
William Kelly ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Latency ◽  
On Chip ◽  
Soi Cmos
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