The U1traSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor

2006 ◽  
Author(s):  
Ana Sonia Leon ◽  
Denis Sheahan
Keyword(s):  
High Throughput ◽  
Power Efficient

A Power-Efficient High-Throughput 32-Thread SPARC Processor

2007 ◽  
Vol 42 (1) ◽  
pp. 7-16 ◽  
Author(s):  
Ana Sonia Leon ◽  
Kenway W. Tam ◽  
Jinuk Luke Shin ◽  
David Weisner ◽  
Francis Schumacher
Keyword(s):  
High Throughput ◽  
Power Efficient

scholarly journals Design o f “ 32 ” Point Split Radix b ased Multipath Delay Commutator FFT Architecture for Low Power Applications

2018 ◽  
Vol 11 (3) ◽  
pp. 1042
Author(s):  
A. Manimaran ◽  
ABY K. Thomas
Keyword(s):  
Signal Processing ◽  
High Throughput ◽  
High Speed ◽  
Power Saving ◽  
Conjugate Pair ◽  
Processing Application ◽  
Power Efficient ◽  
Complex Design ◽  
Operational Modes ◽  
Multipath Delay

<p>FFT is used in Modern high speed signal processing application. In aforementioned technologies that tends to operate in various operational modes. To implement FFT obviously it not only needs to meet high throughput demand and also it needed to scalable cater selectable N point FFT. Our contribution to this paper is two-fold of our existing method, as proposes for the split radix using Multipath Delay Commutator (MDC) algorithm has the least complex design and less multiplications comparing to radix-2 algorithm. So that it can able to reduce power consumption and area than our existing work. The implementation of power efficient hardware of split radix FFT (SRFFT) is built up by pruning excessive computation. Leveraging this potential, a new architecture of a configurable SRFFT processor is first developed so that unnecessary computations, which yield zeros at the output, are pruned. Simulations show that maximum power saving of around 20% is achieved. The proposed algorithm consists of mixed radix butterflies, whose structure is more regular. It has the conjugate-pair version, which requires less memory.</p>

High throughput SRAM design for improved computing in autonomous systems

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Kumar Neeraj ◽  
Jitendra Kumar Das
Keyword(s):  
High Throughput ◽  
High Speed ◽  
Soft Errors ◽  
Autonomous Systems ◽  
Sensor Nodes ◽  
Short Supply ◽  
Content Type ◽  
Power Efficient ◽  
Sram Design ◽  
Level Shifter

PurposeHigh throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.Design/methodology/approachPower efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.FindingsBias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.Originality/valueThe proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator

2018 ◽  
Vol 16 (1) ◽  
pp. 175-192
Author(s):  
Wagner Penny ◽  
Jones Goebel ◽  
Guilherme Paim ◽  
Marcelo Porto ◽  
Luciano Agostini ◽  
...  
Keyword(s):  
Video Coding ◽  
High Throughput ◽  
Standard Sample ◽  
Hardware Design ◽  
Power Efficient
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