Defect reduction methodology for advanced copper dual damascene oxide etch

2002 ◽  
Author(s):  
P. Biolsi ◽  
S. Ellinger ◽  
D. Morvay
Keyword(s):  
Defect Reduction ◽  
Dual Damascene

Defect reduction in Cu dual damascene process using short-loop test structures

2003 ◽  
Vol 16 (3) ◽  
pp. 446-451 ◽  
Author(s):  
H. Nagaishi ◽  
M. Fukui ◽  
H. Asakura ◽  
A. Sugimoto
Keyword(s):  
Defect Reduction ◽  
Dual Damascene ◽  
Damascene Process ◽  
Short Loop

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

2002 ◽  
Vol 716 ◽  
Author(s):  
C. L. Gan ◽  
C. V. Thompson ◽  
K. L. Pey ◽  
W. K. Choi ◽  
F. Wei ◽  
...  
Keyword(s):  
Stress Conditions ◽  
Experimental Characterization ◽  
Contact Lines ◽  
Tree Structures ◽  
Similar Test ◽  
Dual Damascene ◽  
Copper Interconnect ◽  
Test Conditions

AbstractElectromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Defect Reduction in Ring Blank Casting Through Design of Experiments

2015 ◽  
Vol 9 (6) ◽  
pp. 536 ◽  
Author(s):  
P. Kannan ◽  
K. Balasubramanian ◽  
R. Vinayagamoorthy
Keyword(s):  
Design Of Experiments ◽  
Defect Reduction ◽  
Ring Blank

Construction of Defect Reduction System by Improving Wet-end Chemical Retention

2020 ◽  
Vol 74 (4) ◽  
pp. 309-315
Author(s):  
Hiroyuki Oishi ◽  
Koichi Tadaki ◽  
Kazutaka Kasuga
Keyword(s):  
Defect Reduction ◽  
Reduction System ◽  
Chemical Retention

Methodology to Correlate Defect Reduction Systems to Electrical Test Data via Artificially Manufactured Defects

2002 ◽  
Author(s):  
Mike Santana ◽  
Alfredo V. Herrera
Keyword(s):  
Test Data ◽  
Learning Opportunities ◽  
Inspection System ◽  
Navigation Systems ◽  
Defect Inspection ◽  
Defect Reduction ◽  
Electrical Test ◽  
Important System

Abstract This paper describes a methodology for correlating physical defect inspection/navigation systems with electrical bitmap data through the fabrication of artificial defects via reticle alterations or circuit modifications using an inline FIB. The methodology chosen consisted of altering decommissioned reticles to create defects resulting in both open and shorted circuits within areas of an AMD microprocessor cache. The reticles were subsequently scanned using a KLA SL300HR StarLight inspection system to confirm their location, while wafers processed on these reticles were scanned at several layers using standard inline metrology. Finally, the wafers were electrically tested, bitmapped, and physically deprocessed. All defect data was then analyzed and cross-correlated between each system, uncovering some important system deficiencies and learning opportunities. Data and images are included to support the significance and effectiveness of such a methodology.

Intel® Component Diagnostic Technology: Tools and Education for Intel Component Defect Reduction

2004 ◽  
Author(s):  
Julie S. Doll
Keyword(s):  
User Interface ◽  
Data Management ◽  
Contract Manufacturing ◽  
Defect Reduction ◽  
Web Based ◽  
Technology Tools ◽  
Diagnostic Capability ◽  
Diagnostic Technology

Abstract To enable efficient, accurate debug of Intel architecture components to take place within contract manufacturing sites, and to provide alternatives for the removal of Intel components from, Intel is deploying a diagnostic capability and attendant educational collateral known as to achieve these objectives Intel® Component Diagnostic Technology. This paper will describe details of Intel® Component Diagnostic Technology, including the diagnostic fixture and user interface, diagnostic scripts and analytical coverage, data management and reporting, and on-site and Web-based educational offerings.

Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process

2003 ◽  
Vol 150 (1) ◽  
pp. G58 ◽  
Author(s):  
Sang-Yun Lee ◽  
Yong-Bae Kim ◽  
Jeong Soo Byun
Keyword(s):  
Antireflection Coating ◽  
Dual Damascene ◽  
Damascene Process ◽  
193 Nm
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