Real-time implementation of speech recognition using RISC processor core

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1996.552000 ◽

2002 ◽

Author(s):

Ching-Tang Chang ◽

Chung-Tze Chang ◽

Huang-Lin Yang ◽

Hwai-Tsu Chang

Keyword(s):

Speech Recognition ◽

Real Time ◽

Processor Core ◽

Risc Processor

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Customizing and extending an embedded RISC processor core for real-time video compression

Proceedings of the Eighth International Symposium on Signal Processing and Its Applications, 2005. ◽

10.1109/isspa.2005.1580240 ◽

2006 ◽

Author(s):

G. Wang ◽

Z. Salcic ◽

M. Biglari-Abhari

Keyword(s):

Real Time ◽

Video Compression ◽

Processor Core ◽

Risc Processor

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FPGA prototyping of a RISC processor core for embedded applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924027 ◽

2001 ◽

Vol 9 (2) ◽

pp. 241-250 ◽

Cited By ~ 36

Author(s):

M. Gschwind ◽

V. Salapura ◽

D. Maurer

Keyword(s):

Processor Core ◽

Risc Processor ◽

Embedded Applications

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The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽

10.3390/electronics10040469 ◽

2021 ◽

Vol 10 (4) ◽

pp. 469

Author(s):

Hyun Woo Oh ◽

Ji Kwang Kim ◽

Gwan Beom Hwang ◽

Seung Eun Lee

Keyword(s):

Embedded Systems ◽

Embedded System ◽

Real Time ◽

Line Drawing ◽

Cmos Process ◽

Embedded Processor ◽

Processor Core ◽

Field Programmable ◽

The Embedded System ◽

Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

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