scholarly journals Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

2006 ◽  
Author(s):  
Marjan Karkooti ◽  
Predrag Radosavljevic ◽  
Joseph Cavallaro
Keyword(s):  
High Throughput ◽  
Tradeoff Analysis ◽  
Ldpc Decoder ◽  
Decoder Architecture

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

High-Throughput FPGA-Based QC-LDPC Decoder Architecture

2015 ◽  
Author(s):  
Swapnil Mhaske ◽  
Hojin Kee ◽  
Tai Ly ◽  
Ahsan Aziz ◽  
Predrag Spasojevic
Keyword(s):  
High Throughput ◽  
Ldpc Decoder ◽  
Decoder Architecture

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

2014 ◽  
Vol 61 (9) ◽  
pp. 2738-2746 ◽  
Author(s):  
Chung-Chao Cheng ◽  
Jeng-Da Yang ◽  
Huang-Chang Lee ◽  
Chia-Hsiang Yang ◽  
Yeong-Luh Ueng
Keyword(s):  
High Throughput ◽  
Ldpc Decoder ◽  
Decoder Architecture

High throughput LDPC decoder architecture for DVB-S2

2013 ◽  
Author(s):  
Tae Hun Kim ◽  
Tae Doo Park ◽  
Gun Yeol Park ◽  
Hae Chan Kwon ◽  
Ji Won Jung
Keyword(s):  
High Throughput ◽  
Ldpc Decoder ◽  
Decoder Architecture

A high-throughput LDPC decoder architecture for high-rate WPAN systems

2011 ◽  
Author(s):  
Kyung-Il Baek ◽  
Hanho Lee ◽  
Chang-Seok Choi ◽  
Sangmin Kim ◽  
Gerald E. Sobelman
Keyword(s):  
High Throughput ◽  
High Rate ◽  
Ldpc Decoder ◽  
Decoder Architecture
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