scholarly journals Decimal Multiplication with Efficient Partial Product Generation

2005 ◽  
Author(s):  
M.A. Erle ◽  
E.M. Schwarz ◽  
M.J. Schulte
Keyword(s):  
Partial Product ◽  
Product Generation ◽  
Decimal Multiplication

scholarly journals New Self-Checking Booth Multipliers

2008 ◽  
Vol 18 (3) ◽  
pp. 319-328 ◽  
Author(s):  
Marc Hunger ◽  
Daniel Marienfeld
Keyword(s):  
Error Detection ◽  
The Self ◽  
Partial Product ◽  
Product Generation ◽  
Almost All

New Self-Checking Booth MultipliersThis work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.

Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication

2014 ◽  
Vol 24 (02) ◽  
pp. 1550019
Author(s):  
Osama Al-Khaleel ◽  
Zakaria Al-Qudah ◽  
Mohammad Al-Khaleel ◽  
Raed Bani-Hani ◽  
Christos Papachristou ◽  
...  
Keyword(s):  
High Performance ◽  
State Of The Art ◽  
The State ◽  
Partial Product ◽  
Hardware Implementations ◽  
Array Multipliers ◽  
Decimal Multiplication ◽  
Multiplier Circuit

This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.

Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 147-157 ◽  
Author(s):  
Ahmet Kakacak ◽  
Aydin Emre Guzel ◽  
Ozan Cihangir ◽  
Sezer Gören ◽  
H. Fatih Ugurdag
Keyword(s):  
Partial Product ◽  
Product Generation

scholarly journals Efficient Realization of BCD Multipliers Using FPGAs

2017 ◽  
Vol 2017 ◽  
pp. 1-12 ◽  
Author(s):  
Shuli Gao ◽  
Dhamin Al-Khalili ◽  
J. M. Pierre Langlois ◽  
Noureddine Chabini
Keyword(s):  
Critical Path ◽  
Partial Product ◽  
Resource Usage ◽  
Path Delay ◽  
Delay Reduction ◽  
Binary Operations ◽  
Critical Path Delay ◽  
Product Generation ◽  
Improved Performance ◽  
Efficient Realization

In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.

Partial product generation for unbalanced ternary signed multiplication

2019 ◽  
Vol 8 (4) ◽  
pp. 238 ◽  
Author(s):  
Samira Din Mohammadi ◽  
Reza Faghih Mirzaee ◽  
Keivan Navi
Keyword(s):  
Partial Product ◽  
Product Generation
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