Revisiting SRT quotient digit selection

2004 ◽  
Author(s):  
P. Kornerup
Keyword(s):  
Quotient Digit

A Fast Radix-4 Floating-Point Divider with Quotient Digit Selection by Comparison Multiples

2006 ◽  
Vol 50 (1) ◽  
pp. 81-92 ◽  
Author(s):  
H. Nikmehr ◽  
B. Phillips ◽  
C.-C. Lim
Keyword(s):  
Floating Point ◽  
Quotient Digit

scholarly journals Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

2013 ◽  
Vol 2013 ◽  
pp. 1-16
Author(s):  
Malte Baesler ◽  
Sven-Ole Voigt
Keyword(s):  
Fixed Point ◽  
The Other ◽  
Floating Point ◽  
Selection Function ◽  
Data Format ◽  
The Third ◽  
Recurrence Algorithm ◽  
Quotient Digit ◽  
Three Components

Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carry-propagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.

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