Wideband approach of the fully integrated transmitter front-end with high power-added efficiency

2007 ◽  
Author(s):  
Hyungrak Kim ◽  
Young Joong Yoon
Keyword(s):  
High Power ◽  
Fully Integrated ◽  
Power Added Efficiency ◽  
Front End

scholarly journals Analysis and Design of a Fully-Integrated High-Power Differential CMOS T/R Switch and Power Amplifier Using Multi-Section Impedance Transformation Technique

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1028
Author(s):  
Hyun-Woong Kim ◽  
Minsik Ahn ◽  
Ockgoo Lee ◽  
Hyoungsoo Kim ◽  
Hyungwook Kim ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Power ◽  
Cmos Process ◽  
Load Impedance ◽  
Power Differential ◽  
Analysis And Design ◽  
Power Added Efficiency ◽  
Front End ◽  
Power Handling Capability ◽  
Voltage Swing

In this paper, a new topology for a high-power single-pole-double-throw (SPDT) antenna switch is presented, and its loss mechanisms are fully analyzed. The differential architecture is employed in the proposed switch implementation to prevent unwanted channel formations of OFF-state Rx switch transistors by relieving the voltage swing over the Rx switch devices. In addition to that, the load impedance seen by the Tx switch is stepped down to reduce the voltage swing even more, allowing the antenna switch to handle a high-power signal without distortions. To drop the switch operating impedance, two matching networks are required at the input and the output of the Tx switch, respectively, and they are carefully implemented considering the integration issue of the front-end circuitries. From the loss analysis of the whole signal path, an optimum switch operating impedance is decided in view of a trade-off between power handling capability and insertion loss of the antenna switch. The insertion loss of the proposed design is compared to the conventional design with electromagnetic (EM) simulated transformer and inductors. The proposed antenna switch is implemented in a standard 0.18 µm CMOS process, and all switch devices adopt the deep n-well structure. The measured performance of the proposed transmitter front-end chain shows a 1 dB compression point (P1dB) of 32.1 dBm with 38.3% power-added efficiency (PAE) at 1.9 GHz.

AlInAs/GaInAs on InP HEMTs for low power supply voltage operation of high power-added efficiency microwave amplifiers

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  
Keyword(s):  
Low Power ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Power Added Efficiency ◽  
Microwave Amplifiers

scholarly journals An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Process Variations ◽  
Calibration Method ◽  
Capacitance Measurement ◽  
Effective Technique ◽  
Fully Integrated ◽  
Front End ◽  
Novel Method ◽  
On Chip

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

2007 ◽  
Vol 42 (6) ◽  
pp. 1310-1317 ◽  
Author(s):  
Massimo Brandolini ◽  
Marco Sosio ◽  
Francesco Svelto
Keyword(s):  
Direct Conversion ◽  
Fully Integrated ◽  
Front End

Fully integrated 60 GHz transceiver in SiGe BiCMOS, RF modules, and 3.6 Gbit/s OFDM data transmission

2011 ◽  
Vol 3 (2) ◽  
pp. 139-145 ◽  
Author(s):  
Srdjan Glisic ◽  
J. Christoph Scheytt ◽  
Yaoming Sun ◽  
Frank Herzel ◽  
Ruoyu Wang ◽  
...  
Keyword(s):  
Data Transmission ◽  
Intermediate Frequency ◽  
Phase Locked Loop ◽  
Data Rate ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Integrated ◽  
Front End ◽  
Free Data ◽  
Bicmos Technology

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.

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