Design and implementation of a low-latency, high-throughput sorted QR decomposition circuit for MIMO communications

2016 ◽  
Author(s):  
Wei-Yang Chen ◽  
Daniel Guenther ◽  
Chung-An Shen ◽  
Gerd Ascheid
Keyword(s):  
High Throughput ◽  
Qr Decomposition ◽  
Low Latency ◽  
Mimo Communications ◽  
Design And Implementation

scholarly journals Multi core processor for QR decomposition based on FPGA

2018 ◽  
Vol 7 (4) ◽  
pp. 2100
Author(s):  
Safaa S. Omran ◽  
Ahmed K. Abdul-abbas
Keyword(s):  
High Throughput ◽  
Hardware Design ◽  
Qr Decomposition ◽  
Low Latency ◽  
Multicore Processor ◽  
Orthogonal Matrices ◽  
Triangular Matrices ◽  
Upper Triangular Matrices ◽  
Givens Rotation ◽  
Multi Core Processor

Hardware design of multicore 32-bits processor is implemented to achieve low latency and high throughput QR decomposition (QRD) based on two algorithms which they are Gram Schmidt (GS) and Givens Rotation (GR). The orthogonal matrices are computed using the first core processor by Gram Schmidt algorithm, and the upper triangular matrices are computed using the second core processor by Givens Rotation algorithm. This design of multicore processor can achieve 50M QRD/s throughput for (4 × 4) matrices at running frequency 200 MHz.  

scholarly journals Design and Implementation of Rearrangable Non-Blocking Switching Network in VLSI

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2858-2863
Keyword(s):  
Interconnection Network ◽  
The Other ◽  
Switching Network ◽  
Low Latency ◽  
Multistage Interconnection Network ◽  
Design And Implementation ◽  
Benes Network ◽  
Benes Networks

The main goal of this article is to implement an effective Non-Blocking Benes switching Network. Benes Switching Network is designed with the uncomplicated switch modules & it’s have so many advantages, small latency, less traffic and it’s required number of switch modules. Clos and Benes networks are play a key role in the class of multistage interconnection network because of their extensibility and mortality. Benes network provides a low latency when compare with the other networks. 8x8 Benes non blocking switching network is designed and synthesized with the using of Xilinx tool 12.1.

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