A low power and compact physical unclonable function based on the cascode current mirrors

2016 ◽  
Author(s):  
Shibang Lin ◽  
Dejian Liang ◽  
Yuan Cao ◽  
Xiaofang Pan ◽  
Xiaojin Zhao
Keyword(s):  
Low Power ◽  
Physical Unclonable Function ◽  
Current Mirrors

scholarly journals Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 27696-27707
Author(s):  
Amin A. Zayed ◽  
Hanady Hussein Issa ◽  
Khaled A. Shehata ◽  
Hani Fikry Ragai
Keyword(s):  
Low Power ◽  
Physical Unclonable Function ◽  
Ultra Low Power ◽  
Power Oscillator

scholarly journals Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function

2020 ◽  
Vol 1 (5) ◽  
Author(s):  
Yasuhiro Takahashi ◽  
Hiroki Koyasu ◽  
S. Dinesh Kumar ◽  
Himanshu Thapliyal
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Electronic Devices ◽  
Random Access ◽  
Cmos Process ◽  
Physical Unclonable Function ◽  
Ultra Low Power ◽  
Measurement Results ◽  
Simulation Results

Abstract Silicon Physical Unclonable Function (PUF) is a general hardware security primitive for security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such radio frequency identification (RFID) and wireless sensor networks (WSN), etc. In this paper, we present a design of 4-bit QUALPUF which is based on static random access memory (SRAM) for low-power portable electronic devices and then shows the post-layout simulation and measurement results. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 $$\upmu$$ μ m standard CMOS process with 1.8 V supply voltage. The 4-bit QUALPUF occupies 58.7$$\times$$ × 15.7 $$\upmu \mathrm {m}^{2}$$ μ m 2 of layout area. The post-layout simulation results illustrate that the uniqueness calculated from the inter-die HDs of the 4-bit QUALPUF is 47.58%, the average reliability is 95.10%, and the the energy dissipation is 29.73 fJ/cycle/bit. The functional measurement results of the fabricated chip are the same as the post-layout simulation results.

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