High performance adaptive routing for Network-on-Chip systems with express highway mechanism

2014 ◽  
Author(s):  
Shih-Chieh Lin ◽  
En-Jui Chang ◽  
Yu-Yin Chen ◽  
Hsien-Kai Hsin ◽  
An-Yeu Andy Wu
Keyword(s):  
High Performance ◽  
Adaptive Routing ◽  
Network On Chip ◽  
On Chip

scholarly journals Congestion aware adaptive routing for network-on-chip communication

2021 ◽  
Author(s):  
Stephen Chui
Keyword(s):  
Embedded Systems ◽  
High Performance ◽  
Data Transfer ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Message Routing ◽  
Data Packets ◽  
Novel Approach ◽  
Communication Links ◽  
On Chip

Network-On-Chip (NoC) has surpassed the traditional bus based on-chip communication in offering better performance for data transfers among many processing, peripheral and other cores of high performance embedded systems. Adaptive routing provides an effective way of efficient on-chip communication among NoC cores. The message routing efficiency can further improve the performance of NoC based embedded systems on a chip. Congestion awareness has been applied to adaptive routing for achieving better data throughput and latency. This thesis presents a novel approach of analyzing congestion to improve NoC throughput by improving packet allocation in NoC routers. The routers would have the knowledge of the traffic conditions around themselves by utilizing the congestion information. We employ header flits to store the congestion information that does not require any additional communication links between the routers. By prioritizing data packets that are likely to suffer the worst congestion would improve overall NoC data transfer latency.

scholarly journals Congestion aware adaptive routing for network-on-chip communication

2021 ◽  
Author(s):  
Stephen Chui
Keyword(s):  
Embedded Systems ◽  
High Performance ◽  
Data Transfer ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Message Routing ◽  
Data Packets ◽  
Novel Approach ◽  
Communication Links ◽  
On Chip

Network-On-Chip (NoC) has surpassed the traditional bus based on-chip communication in offering better performance for data transfers among many processing, peripheral and other cores of high performance embedded systems. Adaptive routing provides an effective way of efficient on-chip communication among NoC cores. The message routing efficiency can further improve the performance of NoC based embedded systems on a chip. Congestion awareness has been applied to adaptive routing for achieving better data throughput and latency. This thesis presents a novel approach of analyzing congestion to improve NoC throughput by improving packet allocation in NoC routers. The routers would have the knowledge of the traffic conditions around themselves by utilizing the congestion information. We employ header flits to store the congestion information that does not require any additional communication links between the routers. By prioritizing data packets that are likely to suffer the worst congestion would improve overall NoC data transfer latency.

scholarly journals Self-Healing Router Approach for High-Performance Network-on-Chip

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Self Healing ◽  
On Chip

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

scholarly journals Six-port optical switch for cluster-mesh photonic network-on-chip

Nanophotonics ◽  
2018 ◽  
Vol 7 (5) ◽  
pp. 827-835 ◽  
Author(s):  
Hao Jia ◽  
Ting Zhou ◽  
Yunchou Zhao ◽  
Yuhao Xia ◽  
Jincheng Dai ◽  
...  
Keyword(s):  
High Performance ◽  
Optical Switching ◽  
Optical Switch ◽  
Optical Signal ◽  
Network On Chip ◽  
Transmission Experiment ◽  
Photonic Network ◽  
Benes Network ◽  
On Chip ◽  
Spectral Responses

AbstractPhotonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

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