A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique

2002 ◽  
Author(s):  
Chiang Jen-Shiun ◽  
Chou Pao-Chu
Keyword(s):  
Fourth Order ◽  
Two Stage ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Gain Compensation ◽  
Compensation Technique

Design of a Fourth-Order Sigma-Delta Modulator for Audio Application

2013 ◽  
Vol 380-384 ◽  
pp. 3580-3583
Author(s):  
Ming Yuan Ren ◽  
Tuo Li ◽  
Chang Chun Dong
Keyword(s):  
High Resolution ◽  
Fourth Order ◽  
High Performance ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

A 99.7-dB DR fourth-order sigma–delta modulator for digital gyroscope sensor

2017 ◽  
Vol 31 (09) ◽  
pp. 1750097 ◽  
Author(s):  
Xin-Peng Di ◽  
Wei-Ping Chen ◽  
Liang Yin ◽  
Xiao-Wei Liu
Keyword(s):  
Fourth Order ◽  
Dynamic Range ◽  
Low Frequency ◽  
Effective Area ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Interface Circuit ◽  
Transconductance Amplifier ◽  
Sample Frequency ◽  
Gyroscope Sensor

A fourth-order single-loop 1-bit sigma–delta [Formula: see text] modulator for digital gyroscope sensor interface circuit is presented in this paper. The effects caused by mismatch between parasite capacitors at the input of the operational transconductance amplifier (OTA) and the nonlinear on-resistance of the CMOS switch are analyzed. The chopping technique is adopted to eliminate the flick noise in low frequency. The modulator is fabricated in a standard CMOS 0.5-[Formula: see text] process and the effective area is 2 mm2. The power dissipation is 9.66 mW when the voltage is 5 V. The tested results show that a 93.7-dB peak signal-to-noise-and-distortion ratio (SNDR) and a 99.7-dB dynamic range (DR) are achievable at the sample frequency of 500 kHz for 2 kHz bandwidth. The optimization of the switches used in the first integrator and the parasite capacity is proved to be effective in the design of modulator.

Sign in / Sign up

Export Citation Format

Share Document