A Canonical Multicore Architecture for Network Routers

Author(s):  
Sabina Grover ◽  
Abhishek Dhanotia ◽  
Gregory T. Byrd
2011 ◽  
Author(s):  
Andrew Z. Brethorst ◽  
Nehal Desai ◽  
Douglas P. Enright ◽  
Ronald Scrofano

Author(s):  
A. S. RADHAMANI ◽  
E. BABURAJ

In recent studies we found that there are many optimization methods presented for multicore processor performance optimization, however each method is suffered from limitations. Hence in this paper we presented a new method which is a combination of bacterial Foraging Particle swarm Optimization with certain constraints named as Constraint based Bacterial Foraging Particle Swarm Optimization (CBFPSO) scheduling can be effectively implemented. The proposed Constraint based Bacterial Foraging Particle Swarm Optimization (CBFPSO) scheduling for multicore architecture, which updates the velocity and position by two bacterial behaviours, i.e. reproduction and elimination dispersal. The performance of CBFPSO is compared with the simulation results of GA, and the result shows that the proposed algorithm has pretty good performance on almost all types of cores compared to GA with respect to completion time and energy consumption.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000926-000951
Author(s):  
Bruce C. Kim ◽  
Sai Evana ◽  
Rahim Kasim

This paper provides development of MEMS switches and packaging of MEMS to test radio frequency circuits used in wireless products such as cell phones and network routers. We discuss fabrication of MEMS using low voltage magnetic materials and their configurations to achieve the optimum switch to test RF low noise amplifiers. We have accomplished a very unique methodology to test low noise amplifiers using built-in sellf-test technique and our MEMS switches are proposed to achieve the verification of low noise amplifiers. Furthermore, we have used MEMS switches that we developed to perform self calibration to correct for the parametric variations and faults within the deep submicron CMOS circuits. We also discuss packaging of MEMS and low noise amplifier using 3D TSV technology.


Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 749
Author(s):  
Hammad Zafar ◽  
Ziaul Haq Abbas ◽  
Ghulam Abbas ◽  
Fazal Muhammad ◽  
Muhammad Tufail ◽  
...  

Named data networking (NDN) is a revolutionary approach to cater for modern and future Internet usage trends. The advancements in web services, social networks and cloud computing have shifted Internet utilization towards information delivery. Information-centric networking (ICN) enables content-awareness in the network layer and adopts name-based routing through the NDN architecture. Data delivery in NDN is receiver-driven pull-based and governed by requests (interests) sent out by the receiver. The ever-increasing share of high-volume media streams traversing the Internet due to the popularity and availability of video-streaming services can put a strain on network resources and lead to congestion. Since most congestion control techniques proposed for NDN are receiver-based and rely on the users to adjust their interest rates, a fairness scheme needs to be implemented at the intermediate network nodes to ensure that “rogue” users do not monopolize the available network resources. This paper proposes a fairness-based active queue management at network routers which performs per-flow interest rate shaping in order to ensure fair allocation of resources. Different congestion scenarios for both single path and multipath network topologies have been simulated to test the effectiveness of the proposed fairness scheme. Performance of the scheme is evaluated using Jain’s fairness index as a fairness metric.


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