A family of very low-power analog building blocks based on CMOS translinear loops

2002 ◽  
Author(s):  
R. Fried ◽  
C. Enz
Keyword(s):  
Low Power ◽  
Building Blocks

Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers

2020 ◽  
Vol 12 (3) ◽  
pp. 168-174
Author(s):  
Rashmi Sahu ◽  
Maitraiyee Konar ◽  
Sudip Kundu
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
High Gain ◽  
The Other ◽  
Operational Amplifiers ◽  
Instrumentation Amplifier ◽  
Biomedical Signals ◽  
Op Amp ◽  
Op Amps ◽  
Multi Stage

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

Low-power building blocks for neural recording systems

2015 ◽  
pp. 400-413
Author(s):  
Mohamed Elzeftawi ◽  
Luke Theogarajan
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
Neural Recording

Design optimization of low-power high-performance DSP building blocks

2004 ◽  
Vol 39 (7) ◽  
pp. 1131-1139 ◽  
Author(s):  
T. Gemmeke ◽  
M. Gansen ◽  
H.J. Stockmanns ◽  
T.G. Noll
Keyword(s):  
Low Power ◽  
Design Optimization ◽  
High Performance ◽  
Building Blocks

scholarly journals Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-13 ◽  
Author(s):  
Jianhong Xiao ◽  
Guang Zhang ◽  
Tianwei Li ◽  
Jose Silva-Martinez
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Building Blocks ◽  
Cmos Technology ◽  
Digital Television ◽  
Main Stream ◽  
Image Rejection ◽  
Fully Integrated ◽  
Front End ◽  
Image Rejection Ratio

A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

scholarly journals Efficient circuit implementation of morlet wavelets

2005 ◽  
Vol 3 (01) ◽  
Author(s):  
M. Meléndez-Rodrí­guez ◽  
J. Silva-Martí­nez ◽  
R. Spencer
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Building Blocks ◽  
Process Parameter ◽  
Circuit Implementation ◽  
Parameter Variations

A family of versatile building blocks intended for the implementation of Morlet wavelets is proposed. The circuits are compact, fully programmable, and well suited for low-voltage and low-power applications. The resulting wavelet is temperature compensated and low sensitive to process parameter variations. Using current sources can independently control the main wavelet parameters. Hspice and breadboard results demonstrate the feasibility of both the wavelet realization and proposed circuits.

scholarly journals Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols

2019 ◽  
pp. 17-61 ◽  
Author(s):  
Utsav Banerjee ◽  
Tenzin S. Ukyab ◽  
Anantha P. Chandrakasan
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Energy Savings ◽  
Logic Gates ◽  
Public Key Cryptography ◽  
Building Blocks ◽  
Modular Arithmetic ◽  
Cmos Process ◽  
Order Of Magnitude ◽  
Low Power Cmos

Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor’s algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present Sapphire – a lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG, provides two orders of magnitude energy savings; a single-port RAM-based number theoretic transform memory architecture is proposed, which provides 124k-gate area savings; while a low-power modular arithmetic unit accelerates polynomial computations. Our test chip was fabricated in TSMC 40nm low-power CMOS process, with the Sapphire cryptographic core occupying 0.28 mm2 area consisting of 106k logic gates and 40.25 KB SRAM. Sapphire can be programmed with custom instructions for polynomial arithmetic and sampling, and it is coupled with a low-power RISC-V micro-processor to demonstrate NIST Round 2 lattice-based CCA-secure key encapsulation and signature protocols Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. All key building blocks of Sapphire are constant-time and secure against timing and simple power analysis side-channel attacks. We also discuss how masking-based DPA countermeasures can be implemented on the Sapphire core without any changes to the hardware.

Novel Architecture for Low-Power CNTFET-Based Compressors

2019 ◽  
Vol 28 (12) ◽  
pp. 1950207 ◽  
Author(s):  
Morteza Dadashi Gavaber ◽  
Mehrdad Poorhosseini ◽  
Saadat Pourmozafari
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Field Effect Transistors ◽  
Critical Path ◽  
Building Blocks ◽  
Cmos Circuits ◽  
Xor Gate ◽  
Speed Reduction ◽  
Different Types ◽  
Power Delay Product

Carbon nanotube field-effect transistors (CNTFETs) are excellent candidates for the replacement of traditional CMOS circuits. One of the most important modules in many arithmetic circuits is multiplier. Sometimes multipliers may occupy more area as well as consume high power which may cause speed reduction in the critical path. Compressors are important building blocks which are used in most multipliers. In this paper, a low-power architecture is proposed which can be used in compressor designs. The proposed architecture uses a low-power three-input XOR gate to reduce area, delay and power consumption. In order to evaluate the delay and power consumption of circuits, we have used four different types of compressors (3–2, 4–2, 5–2 and 7–2). These four designs were simulated using HSPICE simulation tool with 32-nm CMOS model based on 1-V and 1-GHz frequency operator. The results indicate that the proposed compressor architectures have less power–delay product (PDP) and power consumption in comparison with the existing proposed compressors.

scholarly journals A New Low-Voltage Low-Power Dual-Mode VCII-Based SIMO Universal Filter

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 765 ◽  
Author(s):  
Leila Safari ◽  
Gianluca Barile ◽  
Giuseppe Ferri ◽  
Vincenzo Stornelli
Keyword(s):  
Low Power ◽  
Transfer Functions ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Technology ◽  
Universal Filter ◽  
Dual Mode ◽  
Input Multiple Output ◽  
Low Pass

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 μm CMOS technology parameters at a supply voltage of ±0.9 V are provided to support the presented theory.

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