High-efficiency low-power one-clock solutions for multi-clock chips and systems

2002 ◽  
Author(s):  
R. Fried
Keyword(s):  
Low Power ◽  
High Efficiency

scholarly journals Low Power Cusped Field Thruster Developed for the Space-Borne Gravitational Wave Detection Mission in China

2021 ◽  
Vol 11 (14) ◽  
pp. 6549
Author(s):  
Hui Liu ◽  
Ming Zeng ◽  
Xiang Niu ◽  
Hongyan Huang ◽  
Daren Yu
Keyword(s):  
Low Power ◽  
Gravitational Wave ◽  
Attitude Control ◽  
High Efficiency ◽  
Experimental Investigations ◽  
Attitude Control System ◽  
Gravitational Wave Detection ◽  
Wave Detection ◽  
Wide Range ◽  
Institute Of Technology

The microthruster is the crucial device of the drag-free attitude control system, essential for the space-borne gravitational wave detection mission. The cusped field thruster (also called the High Efficiency Multistage Plasma Thruster) becomes one of the candidate thrusters for the mission due to its low complexity and potential long life over a wide range of thrust. However, the prescribed minimum of thrust and thrust noise are considerable obstacles to downscaling works on cusped field thrusters. This article reviews the development of the low power cusped field thruster at the Harbin Institute of Technology since 2012, including the design of prototypes, experimental investigations and simulation studies. Progress has been made on the downscaling of cusped field thrusters, and a new concept of microwave discharge cusped field thruster has been introduced.

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

scholarly journals Wireless Energy Transfer

2015 ◽  
pp. 63-91
Author(s):  
Aya Mabrouki ◽  
Mohamed Latrach
Keyword(s):  
Energy Transfer ◽  
Energy Harvesting ◽  
Low Power ◽  
High Efficiency ◽  
Microwave Energy ◽  
Wireless Energy Transfer ◽  
Design Considerations ◽  
High Efficient ◽  
Harvesting Techniques ◽  
Power Rectifier

This chapter proposes an overview of microwave energy harvesting with focuses on the design of high efficiency low power rectifying circuits. A background survey of RF energy harvesting techniques is presented first. Then, the performances of conventional rectifier topologies are analyzed and discussed. A review of the most efficient rectenna designs, from the state of the art, is also presented. Design considerations for low power rectifier operations are detailed and new high efficient rectifying circuits are designed and evaluated in both GSM and ISM bands under low power constraints.

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

Low-power-pumped high-efficiency frequency doubling at 397.5 nm in a ring cavity

2014 ◽  
Vol 12 (11) ◽  
pp. 111901-111904 ◽  
Author(s):  
Yan Li Yan Li ◽  
Zhiyuan Zhou Zhiyuan Zhou ◽  
Dongsheng Ding Dongsheng Ding ◽  
Baosen Shi Baosen Shi
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Ring Cavity ◽  
Frequency Doubling

Implementation of High-Efficiency and Ultra-Low-Power Transceiver for the Design of Body Channel Communication Applications

2020 ◽  
Vol 39 (12) ◽  
pp. 6034-6057
Author(s):  
Vitawat Sittakul ◽  
S. Vijayalakshmi ◽  
V. Nagarajan ◽  
K. Sakthidasan Sankaran ◽  
Sakthivel Sankaran
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Ultra Low Power
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