scholarly journals RF Receiver Front-End Employing IIP2-Enhanced 25% Duty-Cycle Quadrature Passive Mixer for Advanced Cellular Applications

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 8166-8177 ◽  
Author(s):  
Junghwan Han ◽  
Kuduck Kwon
Keyword(s):  
Duty Cycle ◽  
Passive Mixer ◽  
Rf Receiver ◽  
Front End

scholarly journals Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios

2014 ◽  
Vol 2014 ◽  
pp. 1-20
Author(s):  
Bodhisatwa Sadhu ◽  
Martin Sturm ◽  
Brian M. Sadler ◽  
Ramesh Harjani
Keyword(s):  
Spectrum Sensing ◽  
Circuit Design ◽  
Software Defined Radio ◽  
High Speed ◽  
Cognitive Radios ◽  
Optimization Techniques ◽  
Switched Capacitor ◽  
Rf Receiver ◽  
Front End ◽  
5 Ghz

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.

Low noise amplifier with resistive and capacitive feedback for 2.4 GHz RF receiver front end

2019 ◽  
Vol 25 (2) ◽  
pp. 181-203
Author(s):  
S. Radha ◽  
D.S. Shylu ◽  
P. Nagabushanam ◽  
Jisha Mathew
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Rf Receiver ◽  
Front End ◽  
Noise Amplifier ◽  
Capacitive Feedback

Digital RF receiver front-end with wideband operation capability for m-WiMAX

2011 ◽  
Author(s):  
Heesong Seo ◽  
Inyoung Choi ◽  
Changjoon Park ◽  
Jehyung Yoon ◽  
Bumman Kim
Keyword(s):  
Rf Receiver ◽  
Front End ◽  
Digital Rf

A Low-Current Digitally Predistorted Direct-Conversion Transmitter With 25% Duty-Cycle Passive Mixer

2014 ◽  
Vol 62 (4) ◽  
pp. 726-731 ◽  
Author(s):  
Manel Collados ◽  
HongLi Zhang ◽  
Bernard Tenbroek ◽  
Hsiang-Hui Chang
Keyword(s):  
Duty Cycle ◽  
Direct Conversion ◽  
Passive Mixer

scholarly journals A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1369
Author(s):  
Dongquan Huo ◽  
Luhong Mao ◽  
Liji Wu ◽  
Xiangmin Zhang
Keyword(s):  
Power Consumption ◽  
Flicker Noise ◽  
Analytical Formula ◽  
Direct Conversion ◽  
Low Noise ◽  
Cmos Process ◽  
Passive Mixer ◽  
Dc Offset ◽  
Front End ◽  
Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

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