scholarly journals Constructing Test Suites for Real-Time Embedded Systems Under Input Timing Constraints

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 20920-20937
Author(s):  
Yunlong Sheng ◽  
Shouda Jiang ◽  
Changan Wei
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Timing Constraints ◽  
Test Suites

Task Scheduling under Uncertain Timing Constraints in Real-Time Embedded Systems

2013 ◽  
pp. 211-235 ◽  
Author(s):  
Pranab K. Muhuri ◽  
K. K. Shukla
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Task Scheduling ◽  
Resource Constraints ◽  
Systems Design ◽  
Task Completion ◽  
Timing Constraints ◽  
Timing Constraint ◽  
Processing Times ◽  
And Task

In real-time embedded systems, timeliness of task completion is a very important factor. In such systems, correctness of the output depends on the timely production of results in addition to the logical outcome of computation. Thus, tasks have explicit timing constraints besides other characteristics of general systems, and task scheduling aims towards devising a feasible schedule of the tasks such that timing constraints, resource constraints, precedence constraints, etc. are complied. In real-time embedded systems, the most important timing constraint of a task is the deadline, as tasks must be completed within this time. The next important timing constraint is the processing time, because a task occupies a processor only for this duration of time. However, in the early phase of real-time embedded systems design only an approximate idea of the tasks and their characteristics are known. As a result, uncertainty or impreciseness is associated with the task deadlines and processing times; hence, it is appropriate to use fuzzy numbers to model deadlines and processing times in real-time embedded systems. The chapter introduces a new method using mixed cubic-exponential Hermite interpolation technique for intuitively defining smooth Membership Functions (MFs) for fuzzy deadlines and processing times. The effect of changes in parameterized MFs on the task schedulability and task priorities are explained. Examples are given to demonstrate the significant features and better performance of the new technique.

scholarly journals A Novel Rail-Network Hardware Simulator for Embedded System Programming

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 13
Author(s):  
Balaji M ◽  
Chandrasekaran M ◽  
Vaithiyanathan Dhandapani
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Learning Outcomes ◽  
Real World ◽  
Time Constraints ◽  
Network Simulator ◽  
Practical Applications ◽  
Rail Network ◽  
Knowledge Enhancement

A Novel Rail-Network Hardware with simulation facilities is presented in this paper. The hardware is designed to facilitate the learning of application-oriented, logical, real-time programming in an embedded system environment. The platform enables the creation of multiple unique programming scenarios with variability in complexity without any hardware changes. Prior experimental hardware comes with static programming facilities that focus the students’ learning on hardware features and programming basics, leaving them ill-equipped to take up practical applications with more real-time constraints. This hardware complements and completes their learning to help them program real-world embedded systems. The hardware uses LEDs to simulate the movement of trains in a network. The network has train stations, intersections and parking slots where the train movements can be controlled by using a 16-bit Renesas RL78/G13 microcontroller. Additionally, simulating facilities are provided to enable the students to navigate the trains by manual controls using switches and indicators. This helps them get an easy understanding of train navigation functions before taking up programming. The students start with simple tasks and gradually progress to more complicated ones with real-time constraints, on their own. During training, students’ learning outcomes are evaluated by obtaining their feedback and conducting a test at the end to measure their knowledge acquisition during the training. Students’ Knowledge Enhancement Index is originated to measure the knowledge acquired by the students. It is observed that 87% of students have successfully enhanced their knowledge undergoing training with this rail-network simulator.

scholarly journals NetQoPE: A Model-Driven Network QoS Provisioning Engine for Distributed Real-time and Embedded Systems

2008 ◽  
Author(s):  
Jaiganesh Balasubramanian ◽  
Sumant Tambe ◽  
Balakrishnan Dasarathy ◽  
Shrirang Gadgil ◽  
Frederick Porter ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Qos Provisioning ◽  
Model Driven

scholarly journals The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Line Drawing ◽  
Cmos Process ◽  
Embedded Processor ◽  
Processor Core ◽  
Field Programmable ◽  
The Embedded System ◽  
Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

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