scholarly journals TRNG (True Random Number Generator) Method Using Visible Spectrum for Secure Communication on 5G Network

IEEE Access ◽  
2018 ◽  
Vol 6 ◽  
pp. 12838-12847 ◽  
Author(s):  
Kyungroul Lee ◽  
Sun-Young Lee ◽  
Changho Seo ◽  
Kangbin Yim
Keyword(s):  
Secure Communication ◽  
Random Number ◽  
Random Number Generator ◽  
Visible Spectrum ◽  
Number Generator ◽  
True Random Number Generator ◽  
5G Network

Chaotic True Random Number Generator for Secure Communication Applications

2020 ◽  
Author(s):  
Alaaddin Al-Shidaifat ◽  
Chamindra Jayawickrama ◽  
Yechan Jung ◽  
Songwook-Lee ◽  
Hanjung Song ◽  
...  
Keyword(s):  
Secure Communication ◽  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals Efficient design of chaos based 4 bit true random number generator on FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 1783
Author(s):  
Ramji Gupta ◽  
Alpana Pandey ◽  
R. K.Baghel
Keyword(s):  
Secure Communication ◽  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Experimental Result ◽  
Chaotic Oscillator ◽  
Number Generator ◽  
Efficient Design ◽  
True Random Number Generator

True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite. 

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

2020 ◽  
Vol 14 (7) ◽  
pp. 1001-1011
Author(s):  
Dhirendra Kumar ◽  
Rahul Anand ◽  
Sajai Vir Singh ◽  
Prasanna Kumar Misra ◽  
Ashok Srivastava ◽  
...  
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals A High‐Speed True Random Number Generator Based on a Cu x Te 1− x Diffusive Memristor

2021 ◽  
pp. 2100062
Author(s):  
Kyung Seok Woo ◽  
Jaehyun Kim ◽  
Janguk Han ◽  
Jin Myung Choi ◽  
Woohyun Kim ◽  
...  
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Random Number ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Galois Ring ◽  
Number Generator ◽  
True Random Number Generator ◽  
Number Generation ◽  
Field Programmable ◽  
Gate Array

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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