Dataset Optimization for Real-Time Pedestrian Detection

Due to the limitation of energy consumption and power consumption, the embedded platform cannot meet the real-time requirements of the far-infrared image pedestrian detection algorithm. To solve this problem, this paper proposes a new real-time infrared pedestrian detection algorithm (RepVGG-YOLOv4, Rep-YOLO), which uses RepVGG to reconstruct the YOLOv4 backbone network, reduces the amount of model parameters and calculations, and improves the speed of target detection; using space spatial pyramid pooling (SPP) obtains different receptive field information to improve the accuracy of model detection; using the channel pruning compression method reduces redundant parameters, model size, and computational complexity. The experimental results show that compared with the YOLOv4 target detection algorithm, the Rep-YOLO algorithm reduces the model volume by 90%, the floating-point calculation is reduced by 93.4%, the reasoning speed is increased by 4 times, and the model detection accuracy after compression reaches 93.25%.

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Real-time Pedestrian Detection Algorithm Based on Improved YOLOv3

Journal of Physics Conference Series ◽

10.1088/1742-6596/2002/1/012075 ◽

2021 ◽

Vol 2002 (1) ◽

pp. 012075

Author(s):

Xianchang Xi ◽

Zhikai Huang ◽

Lingyi Ning ◽

Yang Zhang

Keyword(s):

Real Time ◽

Pedestrian Detection ◽

Detection Algorithm

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Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System

Sensors ◽

10.3390/s18041174 ◽

2018 ◽

Vol 18 (4) ◽

pp. 1174 ◽

Cited By ~ 14

Author(s):

Jian Luo ◽

Chang Lin

Keyword(s):

Real Time ◽

Detection System ◽

Pedestrian Detection ◽

Image Sensor ◽

Frame Rate ◽

External Memory ◽

Support Vector ◽

Svm Classification ◽

Prior Art ◽

Memory Modules

In this study, we propose a real-time pedestrian detection system using a FPGA with a digital image sensor. Comparing with some prior works, the proposed implementation realizes both the histogram of oriented gradients (HOG) and the trained support vector machine (SVM) classification on a FPGA. Moreover, the implementation does not use any external memory or processors to assist the implementation. Although the implementation implements both the HOG algorithm and the SVM classification in hardware without using any external memory modules and processors, the proposed implementation’s resource utilization of the FPGA is lower than most of the prior art. The main reasons resulting in the lower resource usage are: (1) simplification in the Getting Bin sub-module; (2) distributed writing and two shift registers in the Cell Histogram Generation sub-module; (3) reuse of each sum of the cell histogram in the Block Histogram Normalization sub-module; and (4) regarding a window of the SVM classification as 105 blocks of the SVM classification. Moreover, compared to Dalal and Triggs’s pure software HOG implementation, the proposed implementation‘s average detection rate is just about 4.05% less, but can achieve a much higher frame rate.

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