Nested Miller compensation in low-power CMOS design

Ka Nang Leung; P.K.T. Mok

doi:10.1109/82.933799

Nested Miller compensation in low-power CMOS design

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/82.933799 ◽

2001 ◽

Vol 48 (4) ◽

pp. 388-394 ◽

Cited By ~ 75

Author(s):

Ka Nang Leung ◽

P.K.T. Mok

Keyword(s):

Low Power ◽

Miller Compensation ◽

Cmos Design ◽

Low Power Cmos ◽

Nested Miller Compensation

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Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349) ◽

10.1109/iscas.1999.780838 ◽

2003 ◽

Author(s):

Ka Nang Leung ◽

P.K.T. Mok ◽

Wing Hung Ki

Keyword(s):

Low Power ◽

Low Voltage ◽

Miller Compensation ◽

Low Power Cmos ◽

Amplifier Design ◽

Cmos Amplifier ◽

Nested Miller Compensation

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Low-power CMOS design through VTH control and low-swing circuits

Proceedings of 1997 International Symposium on Low Power Electronics and Design ◽

10.1145/263272.263273 ◽

1997 ◽

Cited By ~ 14

Author(s):

Takayasu Sakurai ◽

Hiroshi Kawaguchi ◽

Tadahiro Kuroda

Keyword(s):

Low Power ◽

Cmos Design ◽

Low Power Cmos

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Low Power CMOS Design for Radio Frequencies

Ultra-Low Power Wireless Technologies for Sensor Networks ◽

10.1007/978-0-387-49313-8_2 ◽

2007 ◽

pp. 13-39

Keyword(s):

Low Power ◽

Cmos Design ◽

Low Power Cmos ◽

Radio Frequencies

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Low voltage low power CMOS design techniques for deep submicron ICs

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design ◽

10.1109/icvd.2000.812579 ◽

2002 ◽

Cited By ~ 20

Author(s):

Liqiong Wei ◽

K. Roy ◽

V.K. De

Keyword(s):

Low Power ◽

Low Voltage ◽

Deep Submicron ◽

Cmos Design ◽

Low Power Cmos ◽

Design Techniques

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Low power CMOS design strategies

32nd Design Automation Conference ◽

10.1145/196244.196574 ◽

1994 ◽

Cited By ~ 1

Author(s):

Matthias Schoebinger ◽

Tobias G. Noll

Keyword(s):

Low Power ◽

Design Strategies ◽

Cmos Design ◽

Low Power Cmos

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Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design

Proceedings of 1994 IEEE Symposium on Low Power Electronics ◽

10.1109/lpe.1994.573221 ◽

2002 ◽

Cited By ~ 9

Author(s):

T. Indermaur ◽

M. Horowitz

Keyword(s):

Low Power ◽

Cmos Design ◽

Adiabatic Switching ◽

Low Power Cmos ◽

Charge Recovery

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Novel Circuit Technique for Low Power CMOS design

World Academics Journal of Engineering Sciences ◽

10.15449/wjes.2014.2008 ◽

2014 ◽

pp. 2008

Author(s):

Vaibhav Neema

Keyword(s):

Low Power ◽

Cmos Design ◽

Low Power Cmos ◽

Circuit Technique

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Multipath reversed nested Miller compensation with voltage buffer for low-power three-stage amplifiers

2008 IEEE International Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2008.4760676 ◽

2008 ◽

Author(s):

Zushu Yan

Keyword(s):

Low Power ◽

Miller Compensation ◽

Nested Miller Compensation

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A compact three-stage low-voltage low-power BiCMOS operational amplifier with inverted nested Miller compensation

MELECON '98. 9th Mediterranean Electrotechnical Conference. Proceedings (Cat. No.98CH36056) ◽

10.1109/melcon.1998.699439 ◽

2002 ◽

Cited By ~ 1

Author(s):

S. Mayaleh ◽

N.S. Bayindir

Keyword(s):

Low Power ◽

Operational Amplifier ◽

Low Voltage ◽

Miller Compensation ◽

Nested Miller Compensation

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Right-half-plane zero removal technique for low-voltage low-power nested Miller compensation CMOS amplifier

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357) ◽

10.1109/icecs.1999.813179 ◽

2003 ◽

Cited By ~ 4

Author(s):

Ka Nang Leung ◽

P.K.T. Mok ◽

Wing-Hung Ki

Keyword(s):

Low Power ◽

Half Plane ◽

Low Voltage ◽

Miller Compensation ◽

Cmos Amplifier ◽

Removal Technique ◽

Nested Miller Compensation

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