A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs

2000 ◽  
Vol 47 (7) ◽  
pp. 603-613 ◽  
Author(s):  
Huawen Jin ◽  
E.K.F. Lee
Keyword(s):  
Background Calibration ◽  
Calibration Technique ◽  
Timing Error ◽  
Digital Background Calibration ◽  
Time Interleaved

All-digital background calibration technique for timing mismatch of time-interleaved ADCs

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 45-51 ◽  
Author(s):  
Hongmei Chen ◽  
Yunsheng Pan ◽  
Yongsheng Yin ◽  
Fujiang Lin
Keyword(s):  
Background Calibration ◽  
Calibration Technique ◽  
Digital Background Calibration ◽  
Time Interleaved

scholarly journals An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 73
Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Van-Phu Pham ◽  
Cong-Kha Pham
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Dynamic Range ◽  
Analog To Digital Converters ◽  
Background Calibration ◽  
Calibration Technique ◽  
Analog To Digital ◽  
Digital Background Calibration ◽  
Field Programmable ◽  
Time Interleaved

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

scholarly journals A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

VLSI Design ◽  
2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Hongmei Chen ◽  
Yongsheng Yin ◽  
Honghui Deng ◽  
Fujiang Lin
Keyword(s):  
Average Energy ◽  
Low Complexity ◽  
Background Calibration ◽  
Calibration Technique ◽  
Farrow Structure ◽  
Digital Background Calibration ◽  
Sinusoidal Input ◽  
Calibration Algorithm ◽  
Fractional Delay Filter ◽  
Time Interleaved

A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources.

DIGITAL BACKGROUND CALIBRATION FOR TIMING SKEW IN TIME-INTERLEAVED ADC

2014 ◽  
Vol 23 (08) ◽  
pp. 1450117
Author(s):  
JING LI ◽  
YANG LIU ◽  
SHUANGYI WU ◽  
NING NING ◽  
QI YU
Keyword(s):  
Background Calibration ◽  
Least Mean Square ◽  
Frequency Range ◽  
Entire Frequency Range ◽  
Timing Error ◽  
Analog To Digital ◽  
Digital Background Calibration ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Timing Skew

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). The timing error is detected by using the first derivative of the channel ADCs and a least-mean-square (LMS) loop is exploited to compensate the timing skew. The proposed scheme is effective within the entire frequency range of 0–fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes lesser power and smaller area.

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