Comments on "A high speed realization of a residue to binary number system converter"

1998 ◽  
Vol 45 (3) ◽  
pp. 446-447 ◽  
Author(s):  
A. Dhurkadas
Keyword(s):  
High Speed ◽  
Number System ◽  
Binary Number

Non-standard methods for converting numbers from one number system to another

2020 ◽  
Vol 1 (9) ◽  
pp. 28-30
Author(s):  
D. M. Zlatopolski
Keyword(s):  
Binary System ◽  
Maximum Degree ◽  
Number System ◽  
Binary Form ◽  
Binary Number ◽  
Standard Methods ◽  
Optimal Variant ◽  
Decimal System ◽  
Large Numbers ◽  
Independent Work

The article describes a number of little-known methods for translating natural numbers from one number system to another. The first is a method for converting large numbers from the decimal system to the binary system, based on multiple divisions of a given number and all intermediate quotients by 64 (or another number equal to 2n ), followed by writing the last quotient and the resulting remainders in binary form. Then two methods of mutual translation of decimal and binary numbers are described, based on the so-called «Horner scheme». An optimal variant of converting numbers into the binary number system by the method of division by 2 is also given. In conclusion, a fragment of a manuscript from the beginning of the late 16th — early 17th centuries is published with translation into the binary system by the method of highlighting the maximum degree of number 2. Assignments for independent work of students are offered.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

scholarly journals Application of the neural network computing technology for calculating the interval-index characteristics of a minimally redundant modular code

2019 ◽  
Vol 62 (6) ◽  
pp. 652-660
Author(s):  
A. F. Chernyavsky ◽  
A. A. Kolyada ◽  
S. Yu. Protasenya
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
High Speed ◽  
Theoretical Estimate ◽  
Structural Complexity ◽  
Fold Increase ◽  
Number System ◽  
Parallel Structure ◽  
Network Computing ◽  
Time Expenditures

The article is devoted to the problem of creation of high-speed neural networks (NN) for calculation of interval-index characteristics of a minimally redundant modular code. The functional base of the proposed solution is an advanced class of neural networks of a final ring. These neural networks perform position-modular code transformations of scalable numbers using a modified reduction technology. A developed neural network has a uniform parallel structure, easy to implement and requires the time expenditures of the order (3[log2b]+ [log2k]+6tsum  close to the lower theoretical estimate. Here b and k is the average bit capacity and the number of modules respectively; t sum is the duration of the two-place operation of adding integers. The refusal from a normalization of the numbers of the modular code leads to a reduction of the required set of NN of the finite ring on the (k – 1) component. At the same time, the abnormal configuration of minimally redundant modular coding requires an average k-fold increase in the interval index module (relative to the rest of the bases of the modular number system). It leads to an adequate increase in hardware expenses on this module. Besides, the transition from normalized to unregulated coding reduces the level of homogeneity of the structure of the NN for calculating intervalindex characteristics. The possibility of reducing the structural complexity of the proposed NN by using abnormal intervalindex characteristics is investigated.

Complex Binary Number System-based Co-Processor Design for Signal Processing Applications

2021 ◽  
Author(s):  
Sudia Sai Santosh ◽  
Tandyala Sai Swaroop ◽  
Tangudu Kavya ◽  
Ramesh Chinthala
Keyword(s):  
Signal Processing ◽  
Number System ◽  
Binary Number ◽  
Processor Design

Decimal Hardware Multiplier

2018 ◽  
pp. 4607-4618
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Number System ◽  
Floating Point ◽  
Binary Number ◽  
Correct Result ◽  
Fundamental Operation ◽  
Floating Point Arithmetic ◽  
Decimal Arithmetic ◽  
Decimal Numbers ◽  
Decimal Multiplication ◽  
Point Arithmetic

IEEE-754 2008 has extended the standard with decimal floating point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations without being subject to errors caused by decimal to binary conversions. Decimal Multiplication is a fundamental operation utilized in many algorithms and it is referred in the standard IEEE-754 2008. Decimal multiplication has an inherent difficulty associated with the representation of decimal numbers using a binary number system. Both bit and digit carries, as well as invalid results, must be considered in decimal multiplication in order to produce the correct result. This article focuses on algorithms for hardware implementation of decimal multiplication. Both decimal fixed-point and floating-point multiplication are described, including iterative and parallel solutions.

Decimal Hardware Multiplier

2019 ◽  
pp. 722-736
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Number System ◽  
Floating Point ◽  
Binary Number ◽  
Correct Result ◽  
Fundamental Operation ◽  
Floating Point Arithmetic ◽  
Decimal Arithmetic ◽  
Decimal Numbers ◽  
Decimal Multiplication ◽  
Point Arithmetic

IEEE-754 2008 has extended the standard with decimal floating-point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations without being subject to errors caused by decimal to binary conversions. Decimal multiplication is a fundamental operation utilized in many algorithms, and it is referred in the standard IEEE-754 2008. Decimal multiplication has an inherent difficulty associated with the representation of decimal numbers using a binary number system. Both bit and digit carries, as well as invalid results, must be considered in decimal multiplication in order to produce the correct result. This chapter focuses on algorithms for hardware implementation of decimal multiplication. Both decimal fixed-point and floating-point multiplication are described, including iterative and parallel solutions.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

scholarly journals Algorithm for obtaining palindromes of the binary number system

2020 ◽  
Vol 1679 ◽  
pp. 032069
Author(s):  
V V Lyubimov ◽  
R V Melikdzhanyan
Keyword(s):  
Number System ◽  
Binary Number
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