Some circuit design techniques for low-voltage analog functional elements using squaring circuits

1996 ◽  
Vol 43 (7) ◽  
pp. 559-576 ◽  
Author(s):  
K. Kimura
Keyword(s):  
Circuit Design ◽  
Low Voltage ◽  
Functional Elements ◽  
Design Techniques

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

1995 ◽  
Vol 30 (11) ◽  
pp. 1183-1188 ◽  
Author(s):  
T. Yamagata ◽  
S. Tomishima ◽  
M. Tsukude ◽  
T. Tsuruda ◽  
Y. Hashizume ◽  
...  
Keyword(s):  
Circuit Design ◽  
Low Voltage ◽  
Design Techniques

scholarly journals Reliable Low Voltage Circuit Design Techniques

2017 ◽  
Vol 3 (4) ◽  
pp. 32
Author(s):  
P. John Paul ◽  
Raj N
Keyword(s):  
Circuit Design ◽  
Analog Circuits ◽  
Low Voltage ◽  
Floating Gate ◽  
Performance Parameters ◽  
Operational Transconductance Amplifier ◽  
Transconductance Amplifier ◽  
Signal Path ◽  
Simulation Results ◽  
Design Techniques

In this paper, non-conventional circuit design techniques has been reviewed. The techniques discussed are widely used for realizing low voltage low power analog circuits. The discussed techniques in this paper are: Bulk Driven, Floating and Quasi-floating Gate followed by operating of Bulk Driven MOSFET in Floating and Quasi-floating Gate mode. In all the approach, the threshold voltage restriction is removed or reduced from the input signal path thereby reducing the power consumption. However, the adverse effect lies is terms of reduced performance parameters of MOSFET compared to conventional gate driven MOSFET parameters as shown in this paper through simulation results. The comparative analysis of MOSFET parameters results in encouragement of two approaches: Quasi-floating Gate and Bulk Driven Quasi-floating Gate MOSFET. Each of these approaches has its advantage in specific domains. Further in this paper, an Operational Transconductance Amplifier is proposed which use the Bulk Driven Quasi-floating Gate MOSFET technique and the same is amplifier under similar conditions is also realized using Bulk Driven MOSFET so as to highlight the advantage of Bulk Driven  Quasi-floating Gate MOSFET over Bulk Driven MOSFET. All the performances metrics are achieved with the help of HSpice simulator using MOSFET models of 180nm technology provided by UMC.

POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS

2012 ◽  
Vol 21 (06) ◽  
pp. 1240016 ◽  
Author(s):  
TORSTEN LEHMANN ◽  
HOSUNG CHUN ◽  
YUANYUAN YANG
Keyword(s):  
Power Consumption ◽  
Circuit Design ◽  
Power Supply ◽  
Integrated Circuit ◽  
Power Efficiency ◽  
Low Voltage ◽  
Power Saving ◽  
Design Approach ◽  
Electrode Impedance ◽  
Design Techniques

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.

Sign in / Sign up

Export Citation Format

Share Document