scholarly journals Optimization of two-dimensional radome boresight error performance using simulated annealing technique

1993 ◽  
Vol 41 (9) ◽  
pp. 1195-1203 ◽  
Author(s):  
F. Hsu ◽  
P.-R. Chang ◽  
K.-K. Chan
Keyword(s):  
Simulated Annealing ◽  
Two Dimensional ◽  
Error Performance ◽  
Boresight Error

A Simulated Annealing-Based Approach to Three Dimensional Component Packing

1994 ◽  
Author(s):  
Simon Szykman ◽  
Jonathan Cagan
Keyword(s):  
Simulated Annealing ◽  
Three Dimensional ◽  
Packing Problem ◽  
Computational Approach ◽  
Vlsi Circuits ◽  
Two Dimensional ◽  
Optimal Solutions ◽  
Layout Problem ◽  
Component Layout ◽  
General Component

Abstract This paper introduces a computational approach to three dimensional component layout that employs simulated annealing to generate optimal solutions. Simulated annealing has been used extensively for two dimensional layout of VLSI circuits; this research extends techniques developed for two dimensional layout optimization to three dimensional problems which are more representative of mechanical engineering applications. In many of these applications, miniaturization trends increase the need to achieve higher packing density and fit components into smaller containers. This research addresses the three dimensional packing problem, which is a subset of the general component layout problem, as a framework in which to solve general layout problems.

scholarly journals Two-dimensional Placement Using Tabu Search

VLSI Design ◽  
2001 ◽  
Vol 12 (1) ◽  
pp. 13-23
Author(s):  
John M. Emmert ◽  
Dinesh K. Bhatia
Keyword(s):  
Simulated Annealing ◽  
Tabu Search ◽  
Optimization Technique ◽  
Vlsi Design ◽  
Two Dimensional ◽  
Search Technique ◽  
Quality Of Results ◽  
Circuit Performance ◽  
Speed Up

Search based placement of modules is an important problem in VLSI design. It is always desired that the search should converge quickly to a high quality solution. This paper presents a tabu search based optimization technique to place modules on a regular two-dimensional array. The goal of the technique is to speed up the placement process. The technique is based on a two-step placement strategy. The first step is targeted toward improving circuit routability and the second step addresses circuit performance. The technique is demonstrated through placement of several benchmark circuits on academic as well as commercial FPGAs. Results are compared to placements generated by commercial CAE tools and published simulated annealing based techniques. The tabu search technique compares favorably to published simulated annealing based techniques, and it demonstrates an average execution time speedup of 20 with no impact on quality of results when compared to commercial tools.

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