A superconducting microwave linear phase delay line filter

1993 ◽  
Vol 3 (1) ◽  
pp. 2778-2781 ◽  
Author(s):  
F. Huang ◽  
H.C.H. Cheung ◽  
M.J. Lancaster ◽  
R.G. Humphreys ◽  
N.G. Chew ◽  
...  
Keyword(s):  
2014 ◽  
Vol 50 (3) ◽  
pp. 190-192 ◽  
Author(s):  
J.S. Sajin ◽  
G. Praveen ◽  
H.U. Habiba ◽  
P.H. Rao

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Dong Sik Woo ◽  
Young-Ki Cho ◽  
Kang Wook Kim

Amplitude and phase balances of two types of microstrip-(MS-) to-coplanar stripline (CPS) baluns have been analyzed through simulations and measurements, and their effects on broadband antenna performance are investigated. The impedance bandwidth of the balun determined by a back-to-back configuration can sometimes overestimate the balun operating bandwidth. With the conventional balun with a 180° phase delay line, it is observed that the balun balance over the operating frequencies becomes much more improved as the CPS length increases to over 0.1 λg. As compared with the conventional balun, the proposed MS-to-CPS balun demonstrated very wideband performance from 5 to over 20 GHz. With the proposed balun, amplitude and phase imbalances are within 1 dB and ±5°, respectively. Effects of the balun imbalance on overall broadband antenna performance are also discussed with a quasi-Yagi antenna and a narrow beamwidth tapered slot antenna (TSA).


ACTA IMEKO ◽  
2015 ◽  
Vol 4 (3) ◽  
pp. 23 ◽  
Author(s):  
Francesco Lamonaca ◽  
Domenico Luca Carnì ◽  
Domenico Grimaldi

<p>A Hardware Interface (HI) to synchronize the operations of standalone Measurement Instruments (MIs) in the absence of networking has been proposed in the recent literature. The synchronization accuracy achieved is one period of the clock equipping the HI. To improve the synchronization accuracy two solutions can be argued on the basis of the mathematical model of the delay between HIs. The first involves increasing the clock frequency; the second concerns the compensation of the phase delay between HI clocks. In this paper the second solution is adopted in order to: (i) reduce the energy consumption, and (ii) not increase the complexity of the hardware architecture. The phase delay compensation is obtained by introducing a programmable delay line after the HI clocks. The phase delay evaluation and the successive tuning of the delay line are performed in the synchronization phase of the HIs. Once synchronized, each HI is moved to the standalone MI to trigger it according to the common sense of time. During the execution of the measurement procedure, networking is not necessary. Experimental tests validate the correct operation of the upgraded HI architecture and indicate that the achievable synchronization accuracy is a low percentage of the HI clock period.</p>


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