Designing high-throughput VLC decoder. I. Concurrent VLSI architectures

1992 ◽  
Vol 2 (2) ◽  
pp. 187-196 ◽  
Author(s):  
S.-F. Chang ◽  
D.G. Messerschmitt
Keyword(s):  
High Throughput ◽  
Vlsi Architectures

Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC

2016 ◽  
Vol 25 (05) ◽  
pp. 1650049 ◽  
Author(s):  
Vijay K. Sharma ◽  
Saurabh Kumar ◽  
K. K. Mahapatra
Keyword(s):  
High Throughput ◽  
Unit Area ◽  
Critical Path ◽  
Advanced Encryption Standard ◽  
Vlsi Architectures ◽  
Aes Algorithm ◽  
Composite Field ◽  
Low Energy Consumption ◽  
Field Programmable ◽  
Hardware Efficiency

This paper presents high throughput iterative and pipelined VLSI architectures of the Advanced encryption standard (AES) algorithm based on composite field arithmetic in polynomial basis. A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path. Also, inversion in GF(24) module has been separately optimized. ASIC implementation of our S-box has comparatively low power and low energy consumption. The iterative and pipelined implementations of AES in field programmable gate array (FPGA) and ASIC using proposed S-box have high hardware efficiency in terms of throughput per unit area (slices in FPGA).

scholarly journals Energy-Efficient High-Throughput VLSI Architectures for Product-Like Codes

2019 ◽  
Vol 37 (2) ◽  
pp. 477-485 ◽  
Author(s):  
Christoffer Fougstedt ◽  
Per Larsson-Edefors
Keyword(s):  
High Throughput ◽  
Energy Efficient ◽  
Vlsi Architectures
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