Performance of multistage bus networks for a distributed shared memory multiprocessor

1997 ◽  
Vol 8 (1) ◽  
pp. 82-95 ◽  
Author(s):  
L.N. Bhuyan ◽  
R.R. Iyer ◽  
T. Askar ◽  
A.K. Nanda ◽  
M. Kumar
Keyword(s):  
Shared Memory ◽  
Distributed Shared Memory ◽  
Shared Memory Multiprocessor ◽  
Bus Networks

scholarly journals Cache Coherence Protocols in Distributed Systems

2020 ◽  
Vol 1 (3) ◽  
pp. 92-97
Author(s):  
Hanan Shukur ◽  
Subhi Zeebaree ◽  
Rizgar Zebari ◽  
Omar Ahmed ◽  
Lailan Haji ◽  
...  
Keyword(s):  
Distributed Systems ◽  
Shared Memory ◽  
Cache Coherence ◽  
Distributed Shared Memory ◽  
Data Consistency ◽  
Multiprocessor System ◽  
Cache Coherence Protocols ◽  
Coherence Protocols ◽  
Cache Coherence Protocol ◽  
Shared Memory Multiprocessor

Distributed systems performance is affected significantly by cache coherence protocols due to their role in data consistency maintaining. Also, cache coherent protocols have a great task for keeping the interconnection of caches in a multiprocessor environment. Moreover, the overall performance of distributed shared memory multiprocessor system is influenced by the used cache coherence protocol type. The major challenge of shared memory devices is to maintain the cache coherently. Therefore, in past years many contributions have been presented to address the cache issues and to improve the performance of distributed systems. This paper reviews in a systematic way a number of methods used for the cache-coherent protocols in a distributed system.

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