Stencil printing process development for flip chip interconnect

2000 ◽  
Vol 23 (3) ◽  
pp. 165-170 ◽  
Author(s):  
L. Li ◽  
P. Thompson
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Stencil Printing ◽  
Printing Process

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000729-000734
Author(s):  
Stephen Kenny ◽  
Kai Matejat ◽  
Sven Lamprecht ◽  
Olivier Mann
Keyword(s):  
Copper Alloy ◽  
Flip Chip ◽  
Solder Bump ◽  
Electroless Nickel ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Solder Bumps

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications. This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow. Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues. The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump. Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.

A Two-Stage Optimization Method for the Stencil Printing Process Based on Neural Network and Response Surface Method

2010 ◽  
Vol 156-157 ◽  
pp. 10-17 ◽  
Author(s):  
Er Shun Pan ◽  
Yao Jin ◽  
Zhao Mei ◽  
Ying Wang
Keyword(s):  
Neural Network ◽  
Response Surface ◽  
Response Surface Method ◽  
Model Fitting ◽  
Optimization Method ◽  
Small Sample ◽  
Two Stage ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Method

A stencil printing process (SPP) optimization problem is studied in this paper. Due to the limitation that neural network requires a large number of samples for the accurate model fitting, a two-stage SPP optimization method is proposed. The design interval can be reduced with small sample by using neural network. In this reduced design interval , response surface method is adopted to obtain the accurate mathematical SPP model. The concept of confidence level is introduced to make the proposed model robust. An interactive method is used to solve the model. The proposed method is compared with the one-stage optimization method and the results show that the proposed method achieves a better performance on each objective.

Vibration Analysis Based Modeling and Defect Recognition for Flip Chip Solder Joint Inspection

2000 ◽  
Author(s):  
Sheng Liu ◽  
Dathan Erdahl ◽  
I. Charles Ume
Keyword(s):  
Solder Joint ◽  
Vibration Analysis ◽  
Flip Chip ◽  
Process Development ◽  
Great Promise ◽  
Quality Inspection ◽  
Vibration Frequencies ◽  
Vibration Responses ◽  
Solder Joint Inspection ◽  
Joint Quality

Abstract A novel approach for flip chip solder joint quality inspection based on vibration analysis is presented. Traditional solder joint inspection methods have their limitations when applied to flip chip solder joint quality inspection. The vibration detection method is a new approach which has advantages such as being non-contact, non-destructive, fast and can be used on-line or during process development. In this technique, a flip chip was modeled as a thick plate supported by solder bumps. Changes in solder joint quality produce different vibration responses of flip chip, and change its natural vibration frequencies. In this paper, the vibration frequencies of a flip chip on a ceramic substrate were calculated using the finite element method. Based on vibration analysis, a laser ultrasound and interferometric system was developed for flip chip solder joint quality inspection. In this system, chips with good solder joints can be distinguished from chips with bad joints using their vibration responses and frequencies. Defects recognition methods were developed and tested. Results indicate this approach offers great promise for solder bump inspection in flip chip, BGA and chip scale packages.

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